公开(公告)号：US20100102382A1

公开(公告)日：2010-04-29

申请号：US12447817

申请日：2008-09-26

申请人： Satoru Shimada ,  Yoshikazu Yamaoka ,  Kazunori Fujita ,  Tomonori Tabe

发明人： Satoru Shimada ,  Yoshikazu Yamaoka ,  Kazunori Fujita ,  Tomonori Tabe

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66734 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/513 ,  H01L29/66348 ,  H01L29/7397 ,  H01L29/7809 ,  H01L29/7813

摘要： The invention provides a trench gate type transistor in which the gate leakage current is prevented and the gate capacitance is reduced. A trench is formed in an N− type semiconductor layer. A thin silicon oxide film is formed on a region of the N− type semiconductor layer for the active region of the transistor in the trench. On the other hand, a silicon oxide film which is thicker than the silicon oxide film is formed on a region not for the active region. Furthermore, a leading portion extending from inside the trench onto the outside thereof forms a gate electrode contacting the silicon oxide film. This provides a long distance between the gate electrode at the leading portion and the corner portion of the N− type semiconductor layer, thereby preventing the gate leakage current and reducing the gate capacitance.

摘要翻译： 本发明提供了一种沟槽栅型晶体管，其中栅极漏电流被防止并且栅极电容减小。 在N型半导体层中形成沟槽。 在沟槽中的晶体管的有源区域的N型半导体层的区域上形成薄的氧化硅膜。 另一方面，在不是有源区的区域上形成比氧化硅膜厚的氧化硅膜。 此外，从沟槽内部延伸到其外部的引导部分形成与氧化硅膜接触的栅电极。 这提供了在前导部分的栅电极和N-型半导体层的角部之间的长距离，从而防止栅极漏电流并降低栅极电容。

公开(公告)号：US07646062B2

公开(公告)日：2010-01-12

申请号：US11770337

申请日：2007-06-28

申请人： Yoshikazu Yamaoka ,  Satoru Shimada

发明人： Yoshikazu Yamaoka ,  Satoru Shimada

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L27/10 ,  H01L29/73 ,  H01L29/74 ,  H01L27/148 ,  H01L29/749 ,  H01L29/768 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L29/7816 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66553 ,  H01L29/66621

摘要： A semiconductor device that suppresses partial discharging to a semiconductor substrate caused by local concentration of current. The semiconductor device includes a semiconductor substrate, a gate electrode buried in the semiconductor substrate, a conductor buried in the semiconductor substrate further inward from the gate electrode, a wiring layer formed in the semiconductor substrate in connection with the conductor, and an insulation film arranged between the gate electrode and the conductor. The conductor is higher than the surface of the semiconductor substrate.

摘要翻译： 一种半导体器件，其抑制由局部电流集中引起的对半导体衬底的局部放电。 半导体器件包括半导体衬底，埋在半导体衬底中的栅电极，从栅电极进一步向内埋入半导体衬底中的导体，与该导体连接形成在该半导体衬底中的布线层，以及布置在绝缘膜上的绝缘膜 在栅电极和导体之间。 导体高于半导体衬底的表面。

公开(公告)号：US20070120203A1

公开(公告)日：2007-05-31

申请号：US11604359

申请日：2006-11-27

申请人： Yoshikazu Yamaoka ,  Kazunori Fujita ,  Satoru Shimada ,  Hideki Mizuhara ,  Yasunori Inoue

发明人： Yoshikazu Yamaoka ,  Kazunori Fujita ,  Satoru Shimada ,  Hideki Mizuhara ,  Yasunori Inoue

IPC分类号： H01L29/76

CPC分类号： H01L21/28088 ,  H01L21/28114 ,  H01L21/28247 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966

摘要： A semiconductor device includes a semiconductor substrate on which a source region and a drain region are formed, an insulating film formed on the semiconductor substrate and interposed between the source region and the drain region, a gate electrode formed on the insulating film, metal-bearing particles formed on the interface between the insulation film and the gate electrode, and an insulator which has been changed from a part of metal-bearing particles protruding from an edge of the interface.

摘要翻译： 半导体器件包括其上形成有源极区和漏极区的半导体衬底，形成在半导体衬底上且介于源极区和漏极区之间的绝缘膜，形成在绝缘膜上的栅电极，金属轴承 形成在绝缘膜和栅电极之间的界面上的颗粒以及从界面边缘突出的一部分金属承载颗粒改变的绝缘体。

公开(公告)号：US08076720B2

公开(公告)日：2011-12-13

申请号：US12447817

申请日：2008-09-26

申请人： Satoru Shimada ,  Yoshikazu Yamaoka ,  Kazunori Fujita ,  Tomonori Tabe

发明人： Satoru Shimada ,  Yoshikazu Yamaoka ,  Kazunori Fujita ,  Tomonori Tabe

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/66734 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/513 ,  H01L29/66348 ,  H01L29/7397 ,  H01L29/7809 ,  H01L29/7813

摘要： The invention provides a trench gate type transistor in which the gate leakage current is prevented and the gate capacitance is reduced. A trench is formed in an N− type semiconductor layer. A thin silicon oxide film is formed on a region of the N− type semiconductor layer for the active region of the transistor in the trench. On the other hand, a silicon oxide film which is thicker than the silicon oxide film is formed on a region not for the active region. Furthermore, a leading portion extending from inside the trench onto the outside thereof forms a gate electrode contacting the silicon oxide film. This provides a long distance between the gate electrode at the leading portion and the corner portion of the N− type semiconductor layer, thereby preventing the gate leakage current and reducing the gate capacitance.

摘要翻译： 本发明提供了一种沟槽栅型晶体管，其中栅极漏电流被防止并且栅极电容减小。 在N型半导体层中形成沟槽。 在沟槽中的晶体管的有源区域的N型半导体层的区域上形成薄的氧化硅膜。 另一方面，在不是有源区的区域上形成比氧化硅膜厚的氧化硅膜。 此外，从沟槽内部延伸到其外部的引导部分形成与氧化硅膜接触的栅电极。 这提供了在前导部分的栅电极和N-型半导体层的角部之间的长距离，从而防止栅极漏电流并降低栅极电容。

公开(公告)号：US20130000711A1

公开(公告)日：2013-01-03

申请号：US13616502

申请日：2012-09-14

申请人： Yoshikazu YAMAOKA ,  Shigeo Yata ,  Azumi Umeda ,  Daiji Kanematsu

发明人： Yoshikazu YAMAOKA ,  Shigeo Yata ,  Azumi Umeda ,  Daiji Kanematsu

IPC分类号： H01L31/076

CPC分类号： H01L31/075 ,  H01L31/056 ,  H01L31/076 ,  H01L31/1824 ,  H01L31/202 ,  Y02E10/52 ,  Y02E10/545 ,  Y02E10/548 ,  Y02P70/521

摘要： In order to increase the photoelectric conversion efficiency of a photoelectric conversion device, the photoelectric conversion device (200) is provided with a first intermediate layer (44), which is arranged between a p-type layer (42) and an i-type layer (46) and which has a lower refractive index than refractive indices of the p-type layer (42) or the i-type layer (46), and a second intermediate layer (48), which is arranged between an n-type layer (50) and the i-type layer (46) and which has a lower refractive index than refractive indices of the n-type layer (50) or the i-type layer (46).

摘要翻译： 为了提高光电转换装置的光电转换效率，光电转换装置（200）设置有第一中间层（44），其设置在p型层（42）和i型层 （46），并且其折射率比p型层（42）或i型层（46）的折射率低;以及第二中间层（48），其布置在n型层 （50）和i型层（46）的折射率比所述n型层（I）或所述i型层（46）的折射率低的折射率。

公开(公告)号：US07655974B2

公开(公告)日：2010-02-02

申请号：US11829310

申请日：2007-07-27

申请人： Satoru Shimada ,  Yoshikazu Yamaoka ,  Kazunori Fujita ,  Tomonori Tabe

发明人： Satoru Shimada ,  Yoshikazu Yamaoka ,  Kazunori Fujita ,  Tomonori Tabe

IPC分类号： H01L29/76

CPC分类号： H01L21/761 ,  H01L21/763 ,  H01L27/088 ,  H01L29/1087 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/66734 ,  H01L29/7809 ,  H01L29/7813

摘要： A semiconductor device that reduces the width of an isolation region between semiconductor elements. The semiconductor device includes a semiconductor substrate, an epitaxial layer formed on the semiconductor substrate, a buried layer formed between the semiconductor substrate and the epitaxial layer, a first trench formed in the epitaxial layer so as to surround the buried layer, and an insulation film formed in the first trench.

摘要翻译： 一种半导体器件，其减小半导体元件之间的隔离区域的宽度。 半导体器件包括半导体衬底，形成在半导体衬底上的外延层，形成在半导体衬底和外延层之间的掩埋层，形成在外延层中以围绕掩埋层的第一沟槽，以及绝缘膜 形成在第一个沟槽。

公开(公告)号：US06794283B2

公开(公告)日：2004-09-21

申请号：US09320271

申请日：1999-05-27

申请人： Hiroyuki Watanabe ,  Hideki Mizuhara ,  Shinichi Tanimoto ,  Atsuhiro Nishida ,  Yoshikazu Yamaoka ,  Yasunori Inoue

发明人： Hiroyuki Watanabe ,  Hideki Mizuhara ,  Shinichi Tanimoto ,  Atsuhiro Nishida ,  Yoshikazu Yamaoka ,  Yasunori Inoue

IPC分类号： H01L214763

CPC分类号： H01L21/02126 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/02351 ,  H01L21/31155 ,  H01L21/316 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/7681 ,  H01L21/76825 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device superior in reliability and suitable for microminiaturization is provided. An organic SOG film is formed on a silicon oxide film. Boron ions are implanted into the organic SOG film. By introducing boron ions into the organic SOG film, the organic components in the film are decomposed. Also, the moisture and hydroxyl group included in the film are reduced. After a metal interconnection is embedded in a modified SOG film by the Damascene method, a modified SOG film is formed thereon. Then, contact holes are formed. After a contact hole interconnection is embedded in the contact holes, a modified SOG film and an upper metal interconnection are formed by the Damascene method.

摘要翻译： 提供了可靠性优异并且适合于微型化的半导体器件。 在氧化硅膜上形成有机SOG膜。 将硼离子注入到有机SOG膜中。 通过将硼离子引入有机SOG膜中，膜中的有机成分被分解。 此外，膜中包含的水分和羟基也被还原。 通过镶嵌法将金属互连嵌入改性SOG膜中之后，形成改性SOG膜。 然后，形成接触孔。 在接触孔嵌入接触孔互连后，通过镶嵌法形成改性SOG膜和上金属互连。

公开(公告)号：US5203294A

公开(公告)日：1993-04-20

申请号：US857371

申请日：1992-03-25

申请人： Takao Takemura ,  Yoshikazu Yamaoka ,  Takahide Watanabe

发明人： Takao Takemura ,  Yoshikazu Yamaoka ,  Takahide Watanabe

IPC分类号： F02F5/00 ,  F02B61/04 ,  F02B75/02 ,  F02B75/18 ,  F02B75/20 ,  F02F1/24 ,  F16J9/24

CPC分类号： F16J9/24 ,  F02B61/045 ,  F02B75/20 ,  F02B2075/027 ,  F02B2075/1808 ,  F02B2275/20 ,  F02F2001/245

摘要： A four-cycle internal combustion engine which has one or more horizontally disposed cylinder bores and a piston supported for horizontal reciprocation in each cylinder bore. Each piston includes a ring structure wherein a plurality of compression rings are fitted in corresponding parallel grooves formed on the outer periphery of each piston. A positioning pin for each compression ring is press fitted into the groove of the associated ring in its end gap for positioning and holding the end gap of each compression ring at a point along the outer periphery of the piston outside of the area under the piston axis.

摘要翻译： 具有一个或多个水平设置的缸孔的四冲程内燃机和在每个气缸孔中用于水平往复运动的活塞。 每个活塞包括环形结构，其中多个压缩环装配在形成在每个活塞的外周上的对应的平行槽中。 每个压缩环的定位销在其间隙中压配合在相关联的环的槽中，用于在每个压缩环的端部间隙沿着活塞外部的活塞外侧的点处的位置 。

公开(公告)号：US20130014810A1

公开(公告)日：2013-01-17

申请号：US13614788

申请日：2012-09-13

申请人： Yoshikazu YAMAOKA ,  Shigeo YATA

发明人： Yoshikazu YAMAOKA ,  Shigeo YATA

IPC分类号： H01L31/06

CPC分类号： H01L31/076 ,  Y02E10/548

摘要： In order to increase the photoelectric conversion efficiency of a photoelectric conversion device, a photoelectric conversion device (400), obtained by layering semiconductor layers consisting of a p-type layer (42), an i-type layer (46) and an n-type layer (50), is provided with a first intermediate layer (44) and a second intermediate layer (48), which abut the i-type layer (46) and have refractive indices that increase from the side that abuts the i-type layer (46) to the side that does not abut the i-type layer (46) within a range of refractive indices lower than that of the i-type layer.

摘要翻译： 为了提高光电转换装置的光电转换效率，通过将由p型层（42），i型层（46）和n-型层构成的半导体层分层而获得的光电转换装置（400） 型层（50）具有与i型层（46）抵接的第一中间层（44）和第二中间层（48），并且具有从与i型层 层（46）在不比i型层的折射率低的范围内不与i型层（46）抵接的一侧。

公开(公告)号：US08319281B2

公开(公告)日：2012-11-27

申请号：US11965536

申请日：2007-12-27

申请人： Yoshikazu Yamaoka ,  Satoru Shimada ,  Kazunori Fujita ,  Kazuhiro Sasada

发明人： Yoshikazu Yamaoka ,  Satoru Shimada ,  Kazunori Fujita ,  Kazuhiro Sasada

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/4236 ,  H01L21/2815 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7809 ,  H01L29/7813

摘要： A semiconductor device capable of inhibiting a fabricating process from complication while inhibiting the dielectric strength voltage of a insulating film from reduction is obtained. This semiconductor device includes a groove portion, an insulating film formed on a surface of the groove portion, a gate electrode and a source impurity region, wherein upper ends of the gate electrode, which are portions in contact with the insulating film, are each located at a position identical with or deeper than the range of an impurity introduced from a surface of a semiconductor substrate with respect to the insulating film in order to form the source impurity region and above a lower surface of the source impurity region.

摘要翻译： 可以获得能够在抑制绝缘膜的介电强度电压降低的同时抑制制造工艺的复杂化的半导体器件。 该半导体器件包括沟槽部分，形成在沟槽部分的表面上的绝缘膜，栅极电极和源极杂质区域，其中栅电极的与绝缘膜接触的部分的上端分别位于 在与半导体衬底的表面相对于绝缘膜引入的杂质的范围相同或更深的位置处，以形成源极杂质区域和源极杂质区域的下表面之上。