Patent search ap:("ATI Technologies ULC") AND inv:"Gabriel Wong" Page 1

1.

发明申请
ROUTING LAYER FOR MITIGATING STRESS IN A SEMICONDUCTOR DIE 有权
Title translation: 用于在半导体器件中减轻应力的布线层

公开(公告)号：US20130032941A1

公开(公告)日：2013-02-07

申请号：US13647052

申请日：2012-10-08

Applicant: ATI Technologies ULC

Inventor： Roden Topacio , Gabriel Wong

IPC: H01L23/48 , H01L21/60

CPC classification number: H01L24/17 , H01L23/562 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/33 , H01L2224/0233 , H01L2224/02331 , H01L2224/02375 , H01L2224/02381 , H01L2224/0239 , H01L2224/0401 , H01L2224/05005 , H01L2224/05008 , H01L2224/05012 , H01L2224/05013 , H01L2224/05014 , H01L2224/05015 , H01L2224/05022 , H01L2224/05552 , H01L2224/05553 , H01L2224/05554 , H01L2224/05555 , H01L2224/05559 , H01L2224/05569 , H01L2224/05572 , H01L2224/05582 , H01L2224/05583 , H01L2224/1132 , H01L2224/13007 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/81815 , H01L2924/00013 , H01L2924/01012 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/0104 , H01L2924/01047 , H01L2924/01049 , H01L2924/01051 , H01L2924/01052 , H01L2924/01068 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/351 , H01L2924/3512 , H01L2924/35121 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00012 , H01L2924/00014 , H01L2924/0105 , H01L2924/01083 , H01L2924/01028 , H01L2924/01031

Abstract: A routing layer for a semiconductor die is disclosed. The routing layer includes traces interconnecting integrated circuit bond-pads to UBMs. The routing layer is formed on a layer of dielectric material. The routing layer includes conductive traces arranged underneath the UBMs as to absorb stress from solder bumps attached to the UMBs. Traces beneath the UBMs protect parts of the underlying dielectric material proximate the solder bumps, from the stress.

Abstract translation: 公开了一种用于半导体管芯的布线层。路由层包括将集成电路焊盘与UBM相互连接的迹线。布线层形成在介电材料层上。路由层包括布置在UBM下方的导电迹线，以吸收附着到UMB的焊料凸起的应力。 UBM下面的痕迹可保护靠近焊料凸块的基底电介质材料的部分不受应力影响。

2.

发明授权
Creating interconnects between dies using a cross-over die and through-die vias 有权

公开(公告)号：US11830817B2

公开(公告)日：2023-11-28

申请号：US17085215

申请日：2020-10-30

Applicant: ADVANCED MICRO DEVICES, INC. , ATI TECHNOLOGIES ULC

Inventor： Rahul Agarwal , Raja Swaminathan , Michael S. Alfano , Gabriel H. Loh , Alan D. Smith , Gabriel Wong , Michael Mantor

IPC: H01L23/538 , H01L25/065 , H01L21/50 , H01L27/06

CPC classification number: H01L23/5384 , H01L21/50 , H01L23/5381 , H01L23/5385 , H01L25/0657 , H01L27/0688

Abstract: A semiconductor package includes a first die, a second die, and an interconnect die coupled to a first plurality of through-die vias in the first die and a second plurality of through-die vias in the second die. The interconnect die provides communications pathways the first die and the second die.