公开(公告)号：US20220084914A1

公开(公告)日：2022-03-17

申请号：US17023267

申请日：2020-09-16

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Chi-Tsung CHIU ,  Hui-Ying HSIEH ,  Chun Hao CHIU ,  Chiuan-You DING

IPC分类号： H01L23/495

摘要： A semiconductor package structure is provided. The semiconductor package structure includes a lead frame and passive component. The lead frame includes a paddle and a plurality of leads. The lead frame includes a first surface and a second surface opposite to the first surface. The passive component includes an external connector. A pattern of the external connector is corresponding to a pattern of the plurality of leads of the lead frame.

公开(公告)号：US20210125911A1

公开(公告)日：2021-04-29

申请号：US16664631

申请日：2019-10-25

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Chi-Tsung CHIU ,  Hui-Ying HSIEH ,  Kuo-Hua CHEN ,  Cheng Yuan CHEN

IPC分类号： H01L23/498 ,  H01L23/495 ,  H01L21/768

摘要： A semiconductor package structure includes a base, at least one semiconductor element, a first dielectric layer, a second dielectric layer and a circuit layer. The semiconductor element is disposed on the base and has an upper surface. The first dielectric layer covers at least a portion of a peripheral surface of the semiconductor element and has a top surface. The top surface is non-coplanar with the upper surface of the semiconductor element. The second dielectric layer covers the semiconductor element and the first dielectric layer. The circuit layer extends through the second dielectric layer to electrically connect the semiconductor element.

公开(公告)号：US20190122969A1

公开(公告)日：2019-04-25

申请号：US16156991

申请日：2018-10-10

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Hui Hua LEE ,  Hui-Ying HSIEH ,  Cheng-Hung KO ,  Chi-Tsung CHIU

IPC分类号： H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

摘要： A semiconductor device package includes a metal carrier, a passive device, a conductive adhesive material, a dielectric layer and a conductive via. The metal carrier has a first conductive pad and a second conductive pad spaced apart from the first conductive pad. The first conductive pad and the second conductive pad define a space therebetween. The passive device is disposed on top surfaces of first conductive pad and the second conductive pad. The conductive adhesive material electrically connects a first conductive contact and a second conductive contact of the passive device to the first conductive pad and the second conductive pad respectively. The dielectric layer covers the metal carrier and the passive device and exposes a bottom surface of the first conductive pad and the second conductive pad. The conductive via extends within the dielectric layer and is electrically connected to the first conductive pad and/or the second conductive pad.

公开(公告)号：US20200243427A1

公开(公告)日：2020-07-30

申请号：US16846085

申请日：2020-04-10

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Hui Hua LEE ,  Chun Hao CHIU ,  Hui-Ying Hsieh ,  Kuo-Hua CHEN ,  Chi-Tsung CHIU

IPC分类号： H01L23/495 ,  H01L23/00 ,  H01L23/538 ,  H01L23/498 ,  H01L25/065 ,  H01L21/48 ,  H01L25/16

摘要： A semiconductor device package includes a first conductive base, a first insulation layer and a second insulation layer. The first conductive base has a first surface, a second surface opposite to the first surface and a lateral surface extended between the first surface and the second surface. The lateral surface includes a first portion adjacent to the first surface and a second portion adjacent to the second surface. The first insulation layer comprises a first insulation material. The first insulation layer has a first surface and a second surface opposite to the first surface. The first insulation layer covers the first portion of the lateral surface of the first conductive base. The second insulation layer comprises a second insulation material and covers the second portion of the lateral surface of the first conductive base. The first insulation material is different from the second insulation material.

公开(公告)号：US20180019221A1

公开(公告)日：2018-01-18

申请号：US15649545

申请日：2017-07-13

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Bernd Karl APPELT ,  Kay Stefan ESSIG ,  Chi-Tsung CHIU

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L21/56 ,  H01L23/48 ,  H01L21/768 ,  H01L25/065

CPC分类号： H01L23/3135 ,  H01L21/486 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L21/76805 ,  H01L21/76879 ,  H01L23/145 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/3157 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/32 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/211 ,  H01L2224/215 ,  H01L2224/2518 ,  H01L2224/32146 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06582 ,  H01L2924/01022 ,  H01L2924/01029

摘要： A semiconductor package device includes a first die, an adhesive layer, and an encapsulant layer. The first die comprises a first electrode at a first surface of the first die and a second electrode at a second surface of the first die opposite to the first surface of the first die. The adhesive layer is disposed on the first surface of the first die. The encapsulant layer encapsulates the first die and the adhesive layer, wherein substantially an entire surface of the second electrode is exposed from the encapsulant layer.

公开(公告)号：US20180358276A1

公开(公告)日：2018-12-13

申请号：US16107887

申请日：2018-08-21

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Chi-Tsung CHIU ,  Meng-Jen WANG ,  Cheng-Hsi CHUANG ,  Hui-Ying HSIEH ,  Hui Hua LEE

IPC分类号： H01L23/31 ,  H01L23/00 ,  H01L21/78 ,  H01L21/786 ,  H01L23/13 ,  H01L23/14 ,  H01L23/29 ,  H01L23/492 ,  H01L23/495 ,  H01L23/498 ,  H01L23/538 ,  H01L21/56 ,  H01L25/07

CPC分类号： H01L23/3121 ,  H01L21/561 ,  H01L21/78 ,  H01L21/786 ,  H01L23/13 ,  H01L23/14 ,  H01L23/142 ,  H01L23/29 ,  H01L23/3107 ,  H01L23/3142 ,  H01L23/315 ,  H01L23/492 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49575 ,  H01L23/49582 ,  H01L23/49586 ,  H01L23/49861 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/19 ,  H01L24/24 ,  H01L24/25 ,  H01L24/97 ,  H01L25/074 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24247 ,  H01L2224/2518 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/73267 ,  H01L2224/8385 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/15153 ,  H01L2224/83

摘要： A semiconductor device package includes: (1) a conductive base comprising a sidewall, a cavity defined from a first surface of the conductive base, the cavity having a bottom surface and a depth; (2) a semiconductor die disposed on the bottom surface of the cavity, the semiconductor die having a first surface and a second surface opposite the first surface, the second surface of the semiconductor die bonded to the bottom surface of the cavity; and (3) a first insulating material covering the sidewall of the conductive base and extending to a bottom surface of the conductive base.

公开(公告)号：US20170148746A1

公开(公告)日：2017-05-25

申请号：US15250713

申请日：2016-08-29

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Chi-Tsung CHIU ,  Meng-Jen WANG ,  Cheng-Hsi CHUANG ,  Hui-Ying HSIEH ,  Hui Hua LEE

IPC分类号： H01L23/00 ,  H01L21/78 ,  H01L21/48 ,  H01L21/56 ,  H01L23/495 ,  H01L23/31

CPC分类号： H01L23/3121 ,  H01L21/561 ,  H01L21/78 ,  H01L21/786 ,  H01L23/13 ,  H01L23/14 ,  H01L23/142 ,  H01L23/29 ,  H01L23/3107 ,  H01L23/3142 ,  H01L23/315 ,  H01L23/492 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49575 ,  H01L23/49582 ,  H01L23/49586 ,  H01L23/49861 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/19 ,  H01L24/24 ,  H01L24/25 ,  H01L24/97 ,  H01L25/074 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24247 ,  H01L2224/2518 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/73267 ,  H01L2224/8385 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/15153 ,  H01L2224/83

摘要： A semiconductor device package includes a conductive base, and a cavity defined from a first surface of the conductive base, the cavity having a bottom surface and a depth. A semiconductor die is disposed on the bottom surface of the cavity, the semiconductor die having a first surface and a second surface opposite the first surface. The second surface of the semiconductor die is bonded to the bottom surface of the cavity. A distance between the first surface of the semiconductor die and the first surface of the conductive base is about 20% of the depth of the cavity.

公开(公告)号：US20210020594A1

公开(公告)日：2021-01-21

申请号：US16512132

申请日：2019-07-15

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Chi-Tsung CHIU ,  Hui-Ying HSIEH ,  Hui Hua LEE ,  Cheng Yuan CHEN

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L23/13 ,  H01L21/56

摘要： A semiconductor package structure includes a base material, at least one semiconductor chip, an encapsulant, a depression structure, a redistribution layer and at least one conductive via. The semiconductor chip is disposed on the base material. The encapsulant is disposed on the base material and covers the at least one semiconductor chip. The encapsulant has an outer side surface. The depression structure is disposed adjacent to and exposed from of the outer side surface the encapsulant. The redistribution layer is disposed on the encapsulant. The conductive via is disposed in the encapsulant and electrically connects the semiconductor chip and the redistribution layer.

公开(公告)号：US20170365543A1

公开(公告)日：2017-12-21

申请号：US15621970

申请日：2017-06-13

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Hui Hua LEE ,  Chun Hao CHIU ,  Hui-Ying Hsieh ,  Kuo-Hua CHEN ,  Chi-Tsung CHIU

IPC分类号： H01L23/495

摘要： A semiconductor device package includes a first conductive base, a first insulation layer and a second insulation layer. The first conductive base has a first surface, a second surface opposite to the first surface and a lateral surface extended between the first surface and the second surface. The lateral surface includes a first portion adjacent to the first surface and a second portion adjacent to the second surface. The first insulation layer comprises a first insulation material. The first insulation layer has a first surface and a second surface opposite to the first surface. The first insulation layer covers the first portion of the lateral surface of the first conductive base. The second insulation layer comprises a second insulation material and covers the second portion of the lateral surface of the first conductive base. The first insulation material is different from the second insulation material.

公开(公告)号：US20170365542A1

公开(公告)日：2017-12-21

申请号：US15621968

申请日：2017-06-13

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Kay Stefan ESSIG ,  Chi-Tsung CHIU ,  Hui Hua LEE

IPC分类号： H01L23/495

CPC分类号： H01L23/49575 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49513 ,  H01L23/49517 ,  H01L23/49811 ,  H01L23/49866 ,  H01L23/5386 ,  H01L23/5389 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/24137 ,  H01L2224/24145 ,  H01L2224/24195 ,  H01L2224/24247 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/15153

摘要： A semiconductor device package includes a first conductive base, a first semiconductor die, a dielectric layer, a first patterned conductive layer, and a second patterned conductive layer. The first conductive base defines a first cavity. The first semiconductor die is on a bottom surface of the first cavity. The dielectric layer covers the first semiconductor die, the first surface and the second surface of the first conductive base and fills the first cavity. The first patterned conductive layer is on a first surface of the dielectric layer. The second patterned conductive layer is on a second surface of the dielectric layer.