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1.发明授权
公开(公告)号：US5448424A
公开(公告)日：1995-09-05
申请号：US196478
申请日：1994-02-15
申请人： Akihiko Hirano , Terumi Takashi , Kazunori Iwabuchi , Hideyuki Yamakawa , Yoshiteru Ishida , Minoru Kosuge
发明人： Akihiko Hirano , Terumi Takashi , Kazunori Iwabuchi , Hideyuki Yamakawa , Yoshiteru Ishida , Minoru Kosuge
IPC分类号： G11B5/09 , G11B20/04 , G11B20/10 , G11B20/12 , G11B20/14 , H03G3/00 , H03G3/20 , H03G3/30 , H03G11/00 , G11B5/035
CPC分类号： G11B20/10055 , G11B20/10009 , G11B20/1403 , H03G3/001 , G11B20/1252
摘要： An AGC circuit is provided with a variable gain amplifier which changes an amplification gain of an input signal in accordance with an instruction; an extraction unit for extracting a value of an output of the variable gain amplifier at a predetermined interval; and a variable gain control unit for instructing the amplification gain of the variable gain amplifier in a manner such that the amplitude of the input signal is equal to a predetermined amplitude on the basis of the value extracted by the extraction unit. The variable gain control unit is provided with an error signal output device for squaring the value extracted by the extraction unit and for generating an error signal to instruct the amplification gain of the variable gain amplifier in a manner such that the amplitude of the input signal is equal to a predetermined amplitude on the basis of the square value and a square value just before it; and an integrating device for integrating the error signal from the error signal output device and for instructing the amplification gain of the variable gain amplifier.
摘要翻译： AGC电路设置有根据指令改变输入信号的放大增益的可变增益放大器; 提取单元，用于以预定间隔提取可变增益放大器的输出值; 以及可变增益控制单元，用于以使得输入信号的幅度基于由提取单元提取的值等于预定幅度的方式来指示可变增益放大器的放大增益。 可变增益控制单元设置有误差信号输出装置，用于对由提取单元提取的值进行平方，并产生误差信号，以使得输入信号的振幅为 基于正方形值等于预定幅度和刚好在其前的平方值; 以及用于积分来自误差信号输出装置的误差信号并用于指示可变增益放大器的放大增益的积分装置。
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2.发明授权Information recording/reproducing apparatus having a clock timing extraction circuit for extracting a clock signal from an input data signal 失效具有用于从输入数据信号中提取时钟信号的时钟定时提取电路的信息记录/再现装置
公开(公告)号：US5553104A
公开(公告)日：1996-09-03
申请号：US266779
申请日：1994-06-29
申请人： Terumi Takashi , Akihiko Hirano , Kazunori Iwabuchi , Hideyuki Yamakawa , Yoshiteru Ishida , Kazuhisa Shiraishi , Kazutoshi Ashikawa
发明人： Terumi Takashi , Akihiko Hirano , Kazunori Iwabuchi , Hideyuki Yamakawa , Yoshiteru Ishida , Kazuhisa Shiraishi , Kazutoshi Ashikawa
CPC分类号： H03L7/0996 , G11B20/1403 , G11B27/30 , H03L7/081 , H03L7/183 , H04L7/0337
摘要： A clock timing extraction circuit for use in an information recording/reproducing apparatus has a phase comparator for comparing the reproduced signal with a selected clock signal to generate a phase error signal, a clock signal generation circuit for adjusting frequency to cause the error signal to approach zero according to the phase error signal and outputting a plurality of clock signals having mutually different phase differences, a selection circuit for outputting one of the plurality of clock signals on the basis of a selection signal, a phase difference judgement circuit for determining one of the plurality of clock signals having a minimum phase error (Vdet) and generating a selection signal for selection of the clock signal having the minimum phase difference, and a freeze circuit for blocking an output of the phase comparator until the clock signal having the minimum phase error is selected. The information recording/reproducing apparatus has an AGC circuit for limiting an amplitude of a reproduced signal received from a recording medium, the aforementioned clock timing extraction circuit, and a decoder circuit. The clock timing extraction circuit extracts a clock signal from an output signal of the AGC circuit and the decoder decodes the output signal of the AGC circuit on the basis of the extracted clock signal.
摘要翻译： 用于信息记录/再现装置的时钟定时提取电路具有一个相位比较器，用于将再生信号与所选择的时钟信号进行比较以产生相位误差信号;时钟信号产生电路，用于调整频率以使误差信号接近 根据相位误差信号输出零，并输出具有相互不同的相位差的多个时钟信号，用于基于选择信号输出多个时钟信号中的一个的选择电路，用于确定其中之一的相位差判定电路 具有最小相位误差（Vdet）的多个时钟信号，并且产生用于选择具有最小相位差的时钟信号的选择信号，以及用于阻止相位比较器的输出的冻结电路，直到具有最小相位误差的时钟信号 被选中。 信息记录/重放装置具有用于限制从记录介质接收的再现信号的幅度的AGC电路，上述时钟定时提取电路和解码器电路。 时钟定时提取电路从AGC电路的输出信号中提取时钟信号，解码器根据所提取的时钟信号对AGC电路的输出信号进行解码。
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3.发明授权Adaptive equalization circuit for magnetic recording apparatus having high error immunity 失效用于具有高误码抗扰度的磁记录装置的自适应均衡电路
公开(公告)号：US5414571A
公开(公告)日：1995-05-09
申请号：US961623
申请日：1992-10-16
申请人： Hiromi Matsushige , Minoru Kosuge , Yasuhiro Shimura , Hideki Miyasaka , Satoshi Minoshima , Tsuguji Tachiuchi , Kazunori Iwabuchi , Terumi Takashi , Naoto Matsunami
发明人： Hiromi Matsushige , Minoru Kosuge , Yasuhiro Shimura , Hideki Miyasaka , Satoshi Minoshima , Tsuguji Tachiuchi , Kazunori Iwabuchi , Terumi Takashi , Naoto Matsunami
IPC分类号： H03H15/00 , G11B5/035 , G11B20/10 , G11B20/18 , H03H17/00 , H03H21/00 , H03K5/159 , H04B3/04 , H04L25/03 , G11B5/35 , H03H7/30 , H03H7/40
CPC分类号： G11B20/10037 , G11B20/10009 , G11B20/10046 , G11B5/035 , H03K5/159 , H04L25/03038
摘要： A data reproducing circuit having a magnetic head for reading data from a recording medium, an adaptive equalization circuit for optimizing the waveform of a read signal, a discriminator circuit for discriminating an output signal of the adaptive equalization circuit and outputting a discriminated signal to an upper stage circuit, a format detecting circuit for detecting a pattern of signals written on the recording medium from outputs of the magnetic head, an expected value generating circuit for generating an expected value of the waveform of the read signal in accordance with an output of the adaptive equalization circuit and an output of the discriminator circuit, and an error detecting circuit for generating an error signal representing a difference between an output of the adaptive equalization circuit and an output of the expected value generating circuit. In the data reproducing circuit, the adaptive equalization characteristic of the adaptive equalization circuit is changed when a particular signal pattern on the recording medium is detected, allowing the adaptive equalization operation suitable for the recording medium.
摘要翻译： 一种具有用于从记录介质读取数据的磁头的数据再现电路，用于优化读取信号的波形的自适应均衡电路，用于鉴别自适应均衡电路的输出信号并将鉴别信号输出到上位的鉴频电路 格式检测电路，用于根据磁头的输出来检测写在记录介质上的信号的模式;期望值产生电路，用于根据自适应的输出产生读取信号的波形的期望值 均衡电路和鉴别器电路的输出;以及误差检测电路，用于产生表示自适应均衡电路的输出与预期值产生电路的输出之间的差的误差信号。 在数据再现电路中，当检测到记录介质上的特定信号图案时，自适应均衡电路的自适应均衡特性改变，允许适合于记录介质的自适应均衡操作。
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公开(公告)号：US5572157A
公开(公告)日：1996-11-05
申请号：US21854
申请日：1993-02-24
摘要： Count pulses CTP from a counter 15 are supplied to a phase detector 3 through a two-frequency-divider 17 to produce measurement data N.sub.1 representing a difference in phase from a synchronized peak pulses PK. In a subtractor 4, the measurement data N.sub.1 is compensated with error data Ne from a register 13 in order to reduce the number of steady-state phase errors. An internal phase error .DELTA.N produced by the subtractor 4 is supplied to an LPF 5, undergoing compensation processing in a digital filter 7 thereof. The LPF 5 also includes a phase compensator 6 and a period compensator 8 for compensating a control delay experience by the internal phase error .DELTA.N in the digital filter 7. An integer part OPD1 of counter oscillation period data OPD output by the LPF 5 is used for determining an oscillation period of a counter 15 whereas a fraction part OPD2 thereof is accumulated in a register 12 through an adder 11. An error accumulated in a register 12 is transferred to a register 13 and stored therein as error data Ne. Accordingly, the acquisition time is shortened and the number of steady-state errors is also reduced as well.
摘要翻译： 来自计数器15的计数脉冲CTP通过双分频器17被提供给相位检测器3，以产生表示与同步峰值脉冲PK相位相差的测量数据N1。 在减法器4中，为了减少稳态相位误差的数量，从寄存器13补偿测量数据N1的误差数据Ne。 由减法器4产生的内部相位误差DELTA N被提供给在其数字滤波器7中进行补偿处理的LPF5。 LPF5还包括相位补偿器6和周期补偿器8，用于通过数字滤波器7中的内相位误差DELTA N补偿控制延迟体验。使用由LPF 5输出的计数器振荡周期数据OPD的整数部分OPD1 用于确定计数器15的振荡周期，而其分数部分OPD2通过加法器11积累在寄存器12中。寄存器12中累积的误差被传送到寄存器13并作为误差数据Ne存储。 因此，采集时间缩短，稳态误差的数量也减少。
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公开(公告)号：US5841303A
公开(公告)日：1998-11-24
申请号：US742678
申请日：1996-10-31
摘要： Count pulses CTP from a counter 15 are supplied to a phase detector 3 through a two-frequency-divider 17 to produce measurement data N.sub.1 representing a difference in phase from a synchronized peak pulses PK. In a subtractor 4, the measurement data N.sub.1 is compensated with error data Ne from a register 13 in order to reduce the number of steady-state phase errors. An internal phase error .DELTA.N produced by the subtractor 4 is supplied to an LPF 5, undergoing compensation processing in a digital filter 7 thereof. The LPF 5 also includes a phase compensator 6 and a period compensator for compensating a control delay experience by the internal phase error .DELTA.N in the digital filter 7. An integer part OPD1 of counter oscillation period data OPD output by the LPF 5 is used for determining an oscillation period of a counter 15 whereas a fraction part OPD2 thereof is accumulated in a register 12 through an adder 11. An error accumulated in a register 12 is transferred to a register 13 and stored therein as error data Ne. Accordingly, the acquisition time is shortened and the number of steady-state errors is also reduced as well.
摘要翻译： 来自计数器15的计数脉冲CTP通过双分频器17被提供给相位检测器3，以产生表示与同步峰值脉冲PK相位相差的测量数据N1。 在减法器4中，为了减少稳态相位误差的数量，从寄存器13补偿测量数据N1的误差数据Ne。 由减法器4产生的内部相位误差DELTA N被提供给在其数字滤波器7中进行补偿处理的LPF 5。 LPF5还包括相位补偿器6和周期补偿器，用于通过数字滤波器7中的内部相位误差DELTA N来补偿控制延迟体验。由LPF 5输出的计数器振荡周期数据OPD的整数部分OPD1用于 确定计数器15的振荡周期，而其分数部分OPD2通过加法器11积累在寄存器12中。寄存器12中累积的误差被传送到寄存器13并存储在其中作为误差数据Ne。 因此，采集时间缩短，稳态误差的数量也减少。
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6.发明授权Reproduced signal processing method, reproduced signal processing circuit, and a magnetic storage apparatus 有权再现信号处理方法，再现信号处理电路和磁存储装置
公开(公告)号：US6104331A
公开(公告)日：2000-08-15
申请号：US161734
申请日：1998-09-29
申请人： Yoshiteru Ishida , Naoki Satoh , Terumi Takashi , Akihiko Hirano , Seiichi Mita
发明人： Yoshiteru Ishida , Naoki Satoh , Terumi Takashi , Akihiko Hirano , Seiichi Mita
CPC分类号： G11B19/04 , G11B20/10009 , G11B20/24 , G11B5/012 , G11B23/0007 , G11B5/09
摘要： A reproduced signal processing circuit includes a variable gain amplifier to which a signal read from a medium by a reproducing head is inputted; an analog-to-digital converter for converting a signal outputted from the variable gain amplifier into a digital signal; and a variable frequency oscillator for supplying an operation clock signal to the analog-to-digital converter. A reproduced signal processing method includes the steps of operating a first control loop for controlling the variable gain amplifier; operating at least either one of a second control loop and a third control loop, the second control loop controlling the variable frequency oscillator, the third control loop controlling the variable frequency oscillator; filtering by analog filter means the read signal inputted to the variable gain amplifier; operating at least one of first, second, and third noise detecting operations, the first noise detecting operation detecting presence or absence of a noise by comparing an amplitude of the output signal from the variable gain amplifier with a predetermined threshold value, the second noise detecting operation detecting a noise during an operation period of the second control loop, the third noise detecting operation detecting a noise during an operation period of the third control loop; and changing the range of cutoff frequency of the analog filter means in accordance with a result from at least one of the first, second, and third noise detecting operations, thereby controlling at least one of the first, second, and third control loops.
摘要翻译： 再现信号处理电路包括可变增益放大器，从再现头从介质读取的信号被输入到该可变增益放大器; 用于将从可变增益放大器输出的信号转换为数字信号的模拟 - 数字转换器; 以及用于向模数转换器提供操作时钟信号的可变频率振荡器。 再现信号处理方法包括以下步骤：操作用于控制可变增益放大器的第一控制环路; 操作第二控制回路和第三控制回路中的至少一个，控制可变频率振荡器的第二控制回路，控制可变频率振荡器的第三控制回路; 通过模拟滤波器滤波意味着输入到可变增益放大器的读取信号; 操作第一，第二和第三噪声检测操作中的至少一个，所述第一噪声检测操作通过将来自可变增益放大器的输出信号的幅度与预定阈值进行比较来检测噪声的存在或不存在，第二噪声检测 操作在第二控制回路的操作期间检测噪声，第三噪声检测操作在第三控制回路的操作期间检测噪声; 以及根据第一，第二和第三噪声检测操作中的至少一个的结果改变模拟滤波器装置的截止频率的范围，从而控制第一，第二和第三控制回路中的至少一个。
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公开(公告)号：US20090015960A1
公开(公告)日：2009-01-15
申请号：US12217075
申请日：2008-06-30
IPC分类号： G11B15/46
CPC分类号： G11B19/26
摘要： Embodiments of the invention increase the convenience of a magnetic disk drive for portable use by shortening a period of time required to record a large amount of data, and by increasing the reproduction time, in the magnetic disk drive. In one embodiment, an area between servo data parts is interpolated by servo data parts, each of which stores a burst signal, so that the allocation density of a burst signal is made k times. At the time of write operation in which data is written, only the servo data parts are made use of to perform the servo control while a disk is driven at high rotational speed so as to reduce the recording time. At the time of read operation in which data is reproduced, the servo data parts are made use of to ensure the required precision of the servo control at low rotational speed that is 1/k of the rotational speed at the time of write operation. The reproduction at low rotational speed enables the reduction in power consumption.
摘要翻译： 本发明的实施例通过缩短记录大量数据所需的时间周期以及通过增加磁盘驱动器中的再现时间来增加用于便携式使用的磁盘驱动器的便利性。 在一个实施例中，伺服数据部分之间的区域由伺服数据部分内插，每个伺服数据部分存储脉冲串信号，使得脉冲信号的分配密度为k次。 在写入数据的写入操作时，仅利用伺服数据部分来执行伺服控制，同时以高转速驱动盘，以便减少记录时间。 在再现数据的读取操作时，利用伺服数据部分来确保在写入操作时转速为1 / k的低转速下的伺服控制所要求的精度。 在低转速下的再现能够降低功耗。
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公开(公告)号：US20060227451A1
公开(公告)日：2006-10-12
申请号：US11400579
申请日：2006-04-07
CPC分类号： G11B19/26
摘要： Embodiments of the invention increase the convenience of a magnetic disk drive for portable use by shortening a period of time required to record a large amount of data, and by increasing the reproduction time, in the magnetic disk drive. In one embodiment, an area between servo data parts is interpolated by servo data parts, each of which stores a burst signal, so that the allocation density of a burst signal is made k times. At the time of write operation in which data is written, only the servo data parts are made use of to perform the servo control while a disk is driven at high rotational speed so as to reduce the recording time. At the time of read operation in which data is reproduced, the servo data parts are made use of to ensure the required precision of the servo control at low rotational speed that is 1/k of the rotational speed at the time of write operation. The reproduction at low rotational speed enables the reduction in power consumption.
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公开(公告)号：US20060069845A1
公开(公告)日：2006-03-30
申请号：US11228776
申请日：2005-09-16
申请人： Yoshiteru Ishida , Hitoshi Ogawa , Atsushi Saito , Terumi Takashi
发明人： Yoshiteru Ishida , Hitoshi Ogawa , Atsushi Saito , Terumi Takashi
IPC分类号： G06F12/00
CPC分类号： G11B19/04 , G11B20/10 , G11B27/036 , G11B27/322 , G11B2220/2516
摘要： In one embodiment, a write/read apparatus includes an external interface section for data input; an external interface section for data output; a memory for temporarily storing the data that is input through the external interface section for data input and written on the recording medium and the data that is read from the recording medium and sent to the outside through the external interface section for data output; an address generating section for generating unique addresses associated with physical block addresses of the recording medium; a flag generating section for generating flags for prohibiting overwriting of the data to be written on the recording medium; and a processing section for adding the unique addresses generated in the address generating section to the data that is stored in the memory and that is to be written on the recording medium. The data with the addition of the flags generated in the flag generating section and the unique addresses is written on the recording medium.
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公开(公告)号：US07558931B2
公开(公告)日：2009-07-07
申请号：US11228776
申请日：2005-09-16
申请人： Yoshiteru Ishida , Hitoshi Ogawa , Atsushi Saito , Terumi Takashi
发明人： Yoshiteru Ishida , Hitoshi Ogawa , Atsushi Saito , Terumi Takashi
CPC分类号： G11B19/04 , G11B20/10 , G11B27/036 , G11B27/322 , G11B2220/2516
摘要： In one embodiment, a write/read apparatus includes an external interface section for data input; an external interface section for data output; a memory for temporarily storing the data that is input through the external interface section for data input and written on the recording medium and the data that is read from the recording medium and sent to the outside through the external interface section for data output; an address generating section for generating unique addresses associated with physical block addresses of the recording medium; a flag generating section for generating flags for prohibiting overwriting of the data to be written on the recording medium; and a processing section for adding the unique addresses generated in the address generating section to the data that is stored in the memory and that is to be written on the recording medium. The data with the addition of the flags generated in the flag generating section and the unique addresses is written on the recording medium.
摘要翻译： 在一个实施例中，写入/读取装置包括用于数据输入的外部接口部分; 用于数据输出的外部接口部分; 存储器，用于临时存储通过外部接口部分输入并写入到记录介质上的数据的数据和从记录介质读取的数据，并通过外部接口部分发送到外部进行数据输出; 地址产生部分，用于产生与记录介质的物理块地址相关联的唯一地址; 标志产生部分，用于产生用于禁止重写要写入记录介质的数据的标志; 以及处理部分，用于将在地址生成部分中生成的唯一地址添加到存储在存储器中并被写入记录介质的数据。 在标志生成部分生成的标志和唯一地址的数据被写入记录介质。
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