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    Information recording/reproducing apparatus having a clock timing extraction circuit for extracting a clock signal from an input data signal
    1.
    发明授权
    Information recording/reproducing apparatus having a clock timing extraction circuit for extracting a clock signal from an input data signal 失效
    具有用于从输入数据信号中提取时钟信号的时钟定时提取电路的信息记录/再现装置

    公开(公告)号：US5553104A

    公开(公告)日：1996-09-03

    申请号：US266779

    申请日：1994-06-29

    申请人： Terumi Takashi ,  Akihiko Hirano ,  Kazunori Iwabuchi ,  Hideyuki Yamakawa ,  Yoshiteru Ishida ,  Kazuhisa Shiraishi ,  Kazutoshi Ashikawa

    发明人： Terumi Takashi ,  Akihiko Hirano ,  Kazunori Iwabuchi ,  Hideyuki Yamakawa ,  Yoshiteru Ishida ,  Kazuhisa Shiraishi ,  Kazutoshi Ashikawa

    IPC分类号： G11B20/14 ,  G11B27/30 ,  H03L7/06 ,  H03L7/081 ,  H03L7/099 ,  H03L7/183 ,  H04L7/033 ,  H03D3/24

    CPC分类号： H03L7/0996 ,  G11B20/1403 ,  G11B27/30 ,  H03L7/081 ,  H03L7/183 ,  H04L7/0337

    摘要： A clock timing extraction circuit for use in an information recording/reproducing apparatus has a phase comparator for comparing the reproduced signal with a selected clock signal to generate a phase error signal, a clock signal generation circuit for adjusting frequency to cause the error signal to approach zero according to the phase error signal and outputting a plurality of clock signals having mutually different phase differences, a selection circuit for outputting one of the plurality of clock signals on the basis of a selection signal, a phase difference judgement circuit for determining one of the plurality of clock signals having a minimum phase error (Vdet) and generating a selection signal for selection of the clock signal having the minimum phase difference, and a freeze circuit for blocking an output of the phase comparator until the clock signal having the minimum phase error is selected. The information recording/reproducing apparatus has an AGC circuit for limiting an amplitude of a reproduced signal received from a recording medium, the aforementioned clock timing extraction circuit, and a decoder circuit. The clock timing extraction circuit extracts a clock signal from an output signal of the AGC circuit and the decoder decodes the output signal of the AGC circuit on the basis of the extracted clock signal.

    摘要翻译： 用于信息记录/再现装置的时钟定时提取电路具有一个相位比较器，用于将再生信号与所选择的时钟信号进行比较以产生相位误差信号;时钟信号产生电路，用于调整频率以使误差信号接近 根据相位误差信号输出零，并输出具有相互不同的相位差的多个时钟信号，用于基于选择信号输出多个时钟信号中的一个的选择电路，用于确定其中之一的相位差判定电路 具有最小相位误差（Vdet）的多个时钟信号，并且产生用于选择具有最小相位差的时钟信号的选择信号，以及用于阻止相位比较器的输出的冻结电路，直到具有最小相位误差的时钟信号 被选中。 信息记录/重放装置具有用于限制从记录介质接收的再现信号的幅度的AGC电路，上述时钟定时提取电路和解码器电路。 时钟定时提取电路从AGC电路的输出信号中提取时钟信号，解码器根据所提取的时钟信号对AGC电路的输出信号进行解码。

    Digital signal processor, error detection method, and recording medium reproducer
    6.
    发明授权
    Digital signal processor, error detection method, and recording medium reproducer 失效
    数字信号处理器，错误检测方法和记录介质再现器

    公开(公告)号：US5774470A

    公开(公告)日：1998-06-30

    申请号：US524040

    申请日：1995-09-06

    申请人： Takushi Nishiya ,  Shoichi Miyazawa ,  Kazutoshi Ashikawa ,  Ryushi Shimokawa ,  Seiichi Mita

    发明人： Takushi Nishiya ,  Shoichi Miyazawa ,  Kazutoshi Ashikawa ,  Ryushi Shimokawa ,  Seiichi Mita

    IPC分类号： G06F11/10 ,  G11B20/10 ,  G11B20/18 ,  H03H15/00 ,  H03H17/00 ,  H03H21/00 ,  H03M13/23 ,  H03M13/41 ,  H04B3/04

    CPC分类号： G11B20/10055 ,  G11B20/10009 ,  G11B20/18 ,  H03M13/41 ,  H03M13/6331 ,  H03M13/6505

    摘要： A playback signal processing circuit for reducing decode errors and enabling high-density digital magnetic recording and a digital magnetic recording reproducing unit using the playback signal processing circuit are provided. An estimated waveform generation circuit uses the decoding result of a PRML channel to generate an ideal playback signal waveform. A subtractor provides a waveform representing a difference between the waveform and an actual playback signal. There is a high probability that error bits will occur at an interval of two or four bits because of the nature of GCR code and maximum-likelihood decoding; in the error state of each bit, one bit is incremented by one with respect to the correct bit value and the other signal bit is decremented by one. From this fact, an error detection circuit discriminates an error difference waveform pattern and an error discrimination circuit detects an error bit interval, whereby an error correction circuit carries out error bit correction.

    摘要翻译： 提供了一种用于减少解码错误并实现高密度数字磁记录的重放信号处理电路和使用重放信号处理电路的数字磁记录再现单元。 估计波形生成电路使用PRML通道的解码结果来产生理想的重放信号波形。 减法器提供表示波形和实际重放信号之间的差异的波形。 由于GCR码的性质和最大似然解码，错误位将以两位或四位的间隔发生的概率很高; 在每个位的错误状态下，一个比特相对于正确的比特值递增1，另一个比特递减1。 根据该事实，误差检测电路鉴别误差波形图案，误差鉴别电路检测误差位间隔，由此误差校正电路进行错误位校正。