公开(公告)号：US07521309B2

公开(公告)日：2009-04-21

申请号：US11948344

申请日：2007-11-30

申请人： Akio Kaneko ,  Motoyuki Sato ,  Katsuyuki Sekine ,  Tomohiro Saito ,  Kazuaki Nakajima ,  Tomonori Aoyama

发明人： Akio Kaneko ,  Motoyuki Sato ,  Katsuyuki Sekine ,  Tomohiro Saito ,  Kazuaki Nakajima ,  Tomonori Aoyama

IPC分类号： H01L21/336

CPC分类号： H01L29/517 ,  H01L21/28097 ,  H01L21/3215 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/66507

摘要： A method of manufacturing a semiconductor device having a MOSFET of a first conductivity type and a MOSFET of a second conductivity type different from the first conductivity type formed on a semiconductor substrate, the method has: forming a gate insulating film; forming a first gate electrode layer, and forming a second gate electrode layer; forming a first metal containing layer on said first gate electrode layer and said second gate electrode layer; forming a second metal containing layer for preventing diffusion of a metal on said first metal containing layer; forming a third metal containing layer on said second gate electrode layer from which said first metal containing layer and said second metal containing layer are selectively removed, the third metal containing layer having a thickness different from the thickness of said first metal containing layer in a case where the third metal containing layer contains the same metal or alloy as the metal or alloy contained in said first metal containing layer; and performing a thermal processing, thereby causing reaction between the metal contained in said first metal containing layer and said first gate electrode layer to convert said first gate electrode layer into an alloy and causing reaction between the metal contained in said third metal containing layer and said second gate electrode layer to convert said second gate electrode layer into an alloy, thereby forming gate electrodes of different compositions.

摘要翻译： 一种制造具有第一导电类型的MOSFET的半导体器件的方法和形成在半导体衬底上的与第一导电类型不同的第二导电类型的MOSFET，该方法具有：形成栅极绝缘膜; 形成第一栅电极层，形成第二栅电极层; 在所述第一栅电极层和所述第二栅电极层上形成第一含金属层; 形成用于防止金属在所述第一金属含有层上的扩散的第二含金属层; 在所述第二栅电极层上形成第三金属含有层，从所述第二金属含有层和所述第二金属含有层被选择性地除去，所述第三金属含有层的厚度与所述第一金属含有层的厚度不同 其中所述第三含金属层包含与所述第一含金属层中所含的金属或合金相同的金属或合金; 并进行热处理，从而使包含在所述第一金属含有层中的金属与所述第一栅极电极层之间产生反应，将所述第一栅电极层转换成合金，并引起所述第三金属含有层中含有的金属与所述 第二栅极电极层，以将所述第二栅电极层转换成合金，从而形成不同组成的栅电极。

公开(公告)号：US20080138969A1

公开(公告)日：2008-06-12

申请号：US11948344

申请日：2007-11-30

申请人： Akio Kaneko ,  Motoyuki Sato ,  Katsuyuki Sekine ,  Tomohiro Saito ,  Kazuaki Nakajima ,  Tomonori Aoyama

发明人： Akio Kaneko ,  Motoyuki Sato ,  Katsuyuki Sekine ,  Tomohiro Saito ,  Kazuaki Nakajima ,  Tomonori Aoyama

IPC分类号： H01L21/28

CPC分类号： H01L29/517 ,  H01L21/28097 ,  H01L21/3215 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/66507

摘要： A method of manufacturing a semiconductor device having a MOSFET of a first conductivity type and a MOSFET of a second conductivity type different from the first conductivity type formed on a semiconductor substrate, the method has: forming a gate insulating film; forming a first gate electrode layer, and forming a second gate electrode layer; forming a first metal containing layer on said first gate electrode layer and said second gate electrode layer; forming a second metal containing layer for preventing diffusion of a metal on said first metal containing layer; forming a third metal containing layer on said second gate electrode layer from which said first metal containing layer and said second metal containing layer are selectively removed, the third metal containing layer having a thickness different from the thickness of said first metal containing layer in a case where the third metal containing layer contains the same metal or alloy as the metal or alloy contained in said first metal containing layer; and performing a thermal processing, thereby causing reaction between the metal contained in said first metal containing layer and said first gate electrode layer to convert said first gate electrode layer into an alloy and causing reaction between the metal contained in said third metal containing layer and said second gate electrode layer to convert said second gate electrode layer into an alloy, thereby forming gate electrodes of different compositions.

摘要翻译： 一种制造具有第一导电类型的MOSFET的半导体器件的方法和形成在半导体衬底上的与第一导电类型不同的第二导电类型的MOSFET，该方法具有：形成栅极绝缘膜; 形成第一栅电极层，形成第二栅电极层; 在所述第一栅电极层和所述第二栅电极层上形成第一含金属层; 形成用于防止金属在所述第一金属含有层上的扩散的第二含金属层; 在所述第二栅电极层上形成第三金属含有层，从所述第二金属含有层和所述第二金属含有层选择性地除去所述第三金属含有层，所述第三金属含有层的厚度与所述第一金属含有层的厚度不同 其中所述第三含金属层包含与所述第一含金属层中所含的金属或合金相同的金属或合金; 并进行热处理，从而使包含在所述第一金属含有层中的金属与所述第一栅极电极层之间产生反应，将所述第一栅电极层转换成合金，并引起所述第三金属含有层中含有的金属与所述 第二栅极电极层，以将所述第二栅电极层转换成合金，从而形成不同组成的栅极。

公开(公告)号：US20070278587A1

公开(公告)日：2007-12-06

申请号：US11798068

申请日：2007-05-10

申请人： Tomonori Aoyama ,  Tomohiro Saito ,  Katsuyuki Sekine ,  Kazuaki Nakajima ,  Motoyuki Sato ,  Takuya Kobayashi

发明人： Tomonori Aoyama ,  Tomohiro Saito ,  Katsuyuki Sekine ,  Kazuaki Nakajima ,  Motoyuki Sato ,  Takuya Kobayashi

IPC分类号： H01L29/94

CPC分类号： H01L21/26513 ,  H01L21/26506 ,  H01L21/28079 ,  H01L21/28097 ,  H01L21/28202 ,  H01L21/2822 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/785

摘要： This disclosure concerns a semiconductor device comprising a semiconductor substrate; a gate dielectric film provided on the semiconductor substrate and containing Hf, Si, and O or containing Zr, Si and O; a gate electrode of an n-channel FET provided on the gate dielectric film, the gate electrode being made of nickel silicide containing nickel at a higher content than silicon; an aluminum layer provided at a bottom portion of the gate electrode of the n-channel FET; and a gate electrode of a p-channel FET provided on the gate dielectric film, the gate electrode being made of nickel silicide containing nickel at a higher content than silicon.

摘要翻译： 本公开涉及包括半导体衬底的半导体器件; 设置在半导体衬底上并含有Hf，Si和O或含有Zr，Si和O的栅极电介质膜; 设置在所述栅极电介质膜上的n沟道FET的栅电极，所述栅电极由含有比所述硅含量高的镍的镍硅化物制成; 设置在n沟道FET的栅电极的底部的铝层; 以及设置在所述栅极电介质膜上的p沟道FET的栅电极，所述栅电极由镍含量高于硅的镍的硅化镍制成。

公开(公告)号：US20060273413A1

公开(公告)日：2006-12-07

申请号：US11185678

申请日：2005-07-21

申请人： Motoyuki Sato ,  Katsuyuki Sekine ,  Kazuaki Nakajima ,  Tomohiro Saito ,  Kazuhiro Eguchi ,  Atsushi Yagishita

发明人： Motoyuki Sato ,  Katsuyuki Sekine ,  Kazuaki Nakajima ,  Tomohiro Saito ,  Kazuhiro Eguchi ,  Atsushi Yagishita

IPC分类号： H01L29/94

CPC分类号： H01L21/823462 ,  H01L21/82345 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

摘要： There are provided: a semiconductor substrate including first and second device regions isolated by device isolation regions; a first gate insulating film of a high-k material formed in the first device region; a first gate electrode formed on the first gate insulating film; first source and drain regions formed at both sides of the first gate electrode in the first device region; a second gate insulating film of a high-k material which is different from the high-k material of the first gate insulating film, the second gate insulating film being formed in the second device region; a second gate electrode formed on the second gate insulating film; and second source and drain regions formed at both sides of the second gate electrode in the second device region.

摘要翻译： 提供：包括由器件隔离区域隔离的第一和第二器件区域的半导体衬底; 形成在所述第一器件区域中的高k材料的第一栅极绝缘膜; 形成在第一栅极绝缘膜上的第一栅电极; 形成在第一器件区域中的第一栅电极的两侧的第一源极和漏极区; 与所述第一栅极绝缘膜的高k材料不同的高k材料的第二栅极绝缘膜，所述第二栅极绝缘膜形成在所述第二器件区域中; 形成在所述第二栅极绝缘膜上的第二栅电极; 以及形成在第二器件区域中的第二栅电极的两侧的第二源极和漏极区。

公开(公告)号：US20100065918A1

公开(公告)日：2010-03-18

申请号：US12561862

申请日：2009-09-17

申请人： Daisuke Ikeno ,  Tomonori Aoyama ,  Kazuaki Nakajima ,  Seiji Inumiya ,  Takashi Shimizu ,  Takuya Kobayashi

发明人： Daisuke Ikeno ,  Tomonori Aoyama ,  Kazuaki Nakajima ,  Seiji Inumiya ,  Takashi Shimizu ,  Takuya Kobayashi

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823828

摘要： A semiconductor device includes a semiconductor substrate containing a p-type diffusion layer and an n-type diffusion layer which are separated by an element separation film; a gate insulating film formed on or above the p-type diffusion layer and the n-type diffusion layer of the semiconductor substrate, respectively; a gate electrode containing a metallic film and formed on the gate insulating film; a Ge inclusion formed at an interface between the gate insulating film and the metallic film; and a silicon-containing layer formed on the metallic film.

摘要翻译： 半导体器件包括由元件分离膜分离的包含p型扩散层和n型扩散层的半导体衬底; 分别形成在所述p型扩散层和所述半导体衬底的n型扩散层上或之上的栅绝缘膜; 含有金属膜并形成在栅极绝缘膜上的栅电极; 形成在栅极绝缘膜和金属膜之间的界面处的Ge夹杂物; 以及形成在金属膜上的含硅层。

公开(公告)号：US20100288995A1

公开(公告)日：2010-11-18

申请号：US12728028

申请日：2010-03-19

申请人： Yoshio Ozawa ,  Katsuyuki Sekine ,  Kazuaki Nakajima

发明人： Yoshio Ozawa ,  Katsuyuki Sekine ,  Kazuaki Nakajima

IPC分类号： H01L45/00 ,  H01L21/20

CPC分类号： H01L45/1273 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1625 ,  H01L45/1641

摘要： A semiconductor memory device includes: a lower electrode including a plurality of projections formed on a top surface thereof; an oxide film covering the top surface and made of an oxide of a same metal as a metal contained in the lower electrode; and a resistance variable film provided on the oxide film and being in contact with the oxide film, the projections being buried in the oxide film, and a lower layer portion of the resistance variable film having an oxygen concentration lower than an oxygen concentration of a portion other than the lower layer portion of the resistance variable film.

摘要翻译： 半导体存储器件包括：下电极，其包括形成在其顶表面上的多个突起; 覆盖上表面并由与下部电极中所含的金属相同的金属的氧化物构成的氧化膜; 以及设置在氧化膜上并与氧化膜接触的电阻变化膜，所述突起被埋在氧化物膜中，并且电阻变化膜的下层部分的氧浓度低于部分的氧浓度 除了电阻可变膜的下层部分之外。

公开(公告)号：US20080149932A1

公开(公告)日：2008-06-26

申请号：US11946606

申请日：2007-11-28

申请人： Katsuaki Natori ,  Katsuyuki Sekine ,  Daisuke Nishida ,  Ryota Fujitsuka ,  Masayuki Tanaka ,  Kazuaki Nakajima ,  Yoshio Ozawa ,  Akihito Yamamoto

发明人： Katsuaki Natori ,  Katsuyuki Sekine ,  Daisuke Nishida ,  Ryota Fujitsuka ,  Masayuki Tanaka ,  Kazuaki Nakajima ,  Yoshio Ozawa ,  Akihito Yamamoto

IPC分类号： H01L27/115

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/513 ,  H01L29/7881

摘要： A semiconductor device includes a semiconductor substrate, and a memory cell array provided on the semiconductor substrate and including a plurality of memory cells arranged on the semiconductor substrate, each of the plurality of the memory cells including a first insulating film provided on the semiconductor substrate, a charge storage layer provided on the first insulating film, a second insulating film provided on the charge storage layer, and a control electrode containing metal or metal silicide provided on the charge storage layer via the second insulating film, wherein a corner of a lower part of the control electrode includes semiconductor and fails to contain the metal or the metal silicide in a channel width direction view of the memory cell.

摘要翻译： 半导体器件包括半导体衬底和设置在半导体衬底上并且包括布置在半导体衬底上的多个存储单元的存储单元阵列，多个存储单元中的每一个包括设置在半导体衬底上的第一绝缘膜， 设置在所述第一绝缘膜上的电荷存储层，设置在所述电荷存储层上的第二绝缘膜，以及经由所述第二绝缘膜设置在所述电荷存储层上的含有金属或金属硅化物的控制电极， 的控制电极包括半导体，并且在存储单元的沟道宽度方向视图中不能容纳金属或金属硅化物。

公开(公告)号：US07635891B2

公开(公告)日：2009-12-22

申请号：US11946606

申请日：2007-11-28

申请人： Katsuaki Natori ,  Katsuyuki Sekine ,  Daisuke Nishida ,  Ryota Fujitsuka ,  Masayuki Tanaka ,  Kazuaki Nakajima ,  Yoshio Ozawa ,  Akihito Yamamoto

发明人： Katsuaki Natori ,  Katsuyuki Sekine ,  Daisuke Nishida ,  Ryota Fujitsuka ,  Masayuki Tanaka ,  Kazuaki Nakajima ,  Yoshio Ozawa ,  Akihito Yamamoto

IPC分类号： H01L27/115

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/513 ,  H01L29/7881

摘要： A semiconductor device includes a semiconductor substrate, and a memory cell array provided on the semiconductor substrate and including a plurality of memory cells arranged on the semiconductor substrate, each of the plurality of the memory cells including a first insulating film provided on the semiconductor substrate, a charge storage layer provided on the first insulating film, a second insulating film provided on the charge storage layer, and a control electrode containing metal or metal silicide provided on the charge storage layer via the second insulating film, wherein a corner of a lower part of the control electrode includes semiconductor and fails to contain the metal or the metal silicide in a channel width direction view of the memory cell.

摘要翻译： 半导体器件包括半导体衬底和设置在半导体衬底上并且包括布置在半导体衬底上的多个存储单元的存储单元阵列，多个存储单元中的每一个包括设置在半导体衬底上的第一绝缘膜， 设置在所述第一绝缘膜上的电荷存储层，设置在所述电荷存储层上的第二绝缘膜，以及经由所述第二绝缘膜设置在所述电荷存储层上的含有金属或金属硅化物的控制电极， 的控制电极包括半导体，并且在存储单元的沟道宽度方向视图中不能容纳金属或金属硅化物。

公开(公告)号：US08198155B2

公开(公告)日：2012-06-12

申请号：US12693985

申请日：2010-01-26

申请人： Daisuke Ikeno ,  Tomonori Aoyama ,  Kazuaki Nakajima ,  Seiji Inumiya ,  Takashi Shimizu ,  Takuya Kobayashi

发明人： Daisuke Ikeno ,  Tomonori Aoyama ,  Kazuaki Nakajima ,  Seiji Inumiya ,  Takashi Shimizu ,  Takuya Kobayashi

IPC分类号： H01L21/8234 ,  H01L21/8238 ,  H01L29/51

CPC分类号： H01L21/823842 ,  H01L21/28088 ,  H01L21/823807 ,  H01L21/82385 ,  H01L29/1054 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6659

摘要： A semiconductor device according to an embodiment of the present invention includes an N-type transistor formed in a first region on a substrate, and a P-type transistor formed in a second region on the substrate. The device includes the substrate, a first gate insulation film formed on the substrate in the first and second regions, and containing silicon, a second gate insulation film formed on the first gate insulation film in the first region, and containing first metal and oxygen, a third gate insulation film formed on the first gate insulation film in the second region, and containing second metal different from the first metal and oxygen, a fourth gate insulation film formed on the second and third gate insulation films in the first and second regions, and containing hafnium, and a gate electrode layer formed on the fourth gate insulation film in the first and second regions, and containing metal and nitrogen, a thickness of the gate electrode layer formed in the second region being greater than a thickness of the gate electrode layer formed in the first region.

摘要翻译： 根据本发明的实施例的半导体器件包括形成在衬底上的第一区域中的N型晶体管和形成在衬底上的第二区域中的P型晶体管。 该器件包括衬底，形成在第一和第二区域的衬底上并含有硅的第一栅极绝缘膜，形成在第一区域中的第一栅极绝缘膜上并且包含第一金属和氧的第二栅极绝缘膜， 形成在所述第二区域中的所述第一栅极绝缘膜上并且包含不同于所述第一金属和氧的第二金属的第三栅极绝缘膜，形成在所述第一和第二区域中的所述第二和第三栅极绝缘膜上的第四栅极绝缘膜， 并且含有铪，以及形成在第一和第二区域中的第四栅极绝缘膜上并且包含金属和氮的栅极电极层，在第二区域中形成的栅电极层的厚度大于栅电极的厚度 层形成在第一区域中。

公开(公告)号：US20100187612A1

公开(公告)日：2010-07-29

申请号：US12693985

申请日：2010-01-26

申请人： Daisuke IKENO ,  Tomonori Aoyama ,  Kazuaki Nakajima ,  Seiji Inumiya ,  Takashi Shimizu ,  Takuya Kobayashi

发明人： Daisuke IKENO ,  Tomonori Aoyama ,  Kazuaki Nakajima ,  Seiji Inumiya ,  Takashi Shimizu ,  Takuya Kobayashi

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823842 ,  H01L21/28088 ,  H01L21/823807 ,  H01L21/82385 ,  H01L29/1054 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6659

摘要： A semiconductor device according to an embodiment of the present invention includes an N-type transistor formed in a first region on a substrate, and a P-type transistor formed in a second region on the substrate. The device includes the substrate, a first gate insulation film formed on the substrate in the first and second regions, and containing silicon, a second gate insulation film formed on the first gate insulation film in the first region, and containing first metal and oxygen, a third gate insulation film formed on the first gate insulation film in the second region, and containing second metal different from the first metal and oxygen, a fourth gate insulation film formed on the second and third gate insulation films in the first and second regions, and containing hafnium, and a gate electrode layer formed on the fourth gate insulation film in the first and second regions, and containing metal and nitrogen, a thickness of the gate electrode layer formed in the second region being greater than a thickness of the gate electrode layer formed in the first region.

摘要翻译： 根据本发明的实施例的半导体器件包括形成在衬底上的第一区域中的N型晶体管和形成在衬底上的第二区域中的P型晶体管。 该器件包括衬底，形成在第一和第二区域的衬底上并含有硅的第一栅极绝缘膜，形成在第一区域中的第一栅极绝缘膜上并且包含第一金属和氧的第二栅极绝缘膜， 形成在所述第二区域中的所述第一栅极绝缘膜上并且包含不同于所述第一金属和氧的第二金属的第三栅极绝缘膜，形成在所述第一和第二区域中的所述第二和第三栅极绝缘膜上的第四栅极绝缘膜， 并且含有铪，以及形成在第一和第二区域中的第四栅极绝缘膜上并且包含金属和氮的栅极电极层，在第二区域中形成的栅电极层的厚度大于栅电极的厚度 层形成在第一区域中。