公开(公告)号：US07521309B2

公开(公告)日：2009-04-21

申请号：US11948344

申请日：2007-11-30

申请人： Akio Kaneko ,  Motoyuki Sato ,  Katsuyuki Sekine ,  Tomohiro Saito ,  Kazuaki Nakajima ,  Tomonori Aoyama

发明人： Akio Kaneko ,  Motoyuki Sato ,  Katsuyuki Sekine ,  Tomohiro Saito ,  Kazuaki Nakajima ,  Tomonori Aoyama

IPC分类号： H01L21/336

CPC分类号： H01L29/517 ,  H01L21/28097 ,  H01L21/3215 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/66507

摘要： A method of manufacturing a semiconductor device having a MOSFET of a first conductivity type and a MOSFET of a second conductivity type different from the first conductivity type formed on a semiconductor substrate, the method has: forming a gate insulating film; forming a first gate electrode layer, and forming a second gate electrode layer; forming a first metal containing layer on said first gate electrode layer and said second gate electrode layer; forming a second metal containing layer for preventing diffusion of a metal on said first metal containing layer; forming a third metal containing layer on said second gate electrode layer from which said first metal containing layer and said second metal containing layer are selectively removed, the third metal containing layer having a thickness different from the thickness of said first metal containing layer in a case where the third metal containing layer contains the same metal or alloy as the metal or alloy contained in said first metal containing layer; and performing a thermal processing, thereby causing reaction between the metal contained in said first metal containing layer and said first gate electrode layer to convert said first gate electrode layer into an alloy and causing reaction between the metal contained in said third metal containing layer and said second gate electrode layer to convert said second gate electrode layer into an alloy, thereby forming gate electrodes of different compositions.

摘要翻译： 一种制造具有第一导电类型的MOSFET的半导体器件的方法和形成在半导体衬底上的与第一导电类型不同的第二导电类型的MOSFET，该方法具有：形成栅极绝缘膜; 形成第一栅电极层，形成第二栅电极层; 在所述第一栅电极层和所述第二栅电极层上形成第一含金属层; 形成用于防止金属在所述第一金属含有层上的扩散的第二含金属层; 在所述第二栅电极层上形成第三金属含有层，从所述第二金属含有层和所述第二金属含有层被选择性地除去，所述第三金属含有层的厚度与所述第一金属含有层的厚度不同 其中所述第三含金属层包含与所述第一含金属层中所含的金属或合金相同的金属或合金; 并进行热处理，从而使包含在所述第一金属含有层中的金属与所述第一栅极电极层之间产生反应，将所述第一栅电极层转换成合金，并引起所述第三金属含有层中含有的金属与所述 第二栅极电极层，以将所述第二栅电极层转换成合金，从而形成不同组成的栅电极。

公开(公告)号：US20080138969A1

公开(公告)日：2008-06-12

申请号：US11948344

申请日：2007-11-30

申请人： Akio Kaneko ,  Motoyuki Sato ,  Katsuyuki Sekine ,  Tomohiro Saito ,  Kazuaki Nakajima ,  Tomonori Aoyama

发明人： Akio Kaneko ,  Motoyuki Sato ,  Katsuyuki Sekine ,  Tomohiro Saito ,  Kazuaki Nakajima ,  Tomonori Aoyama

IPC分类号： H01L21/28

CPC分类号： H01L29/517 ,  H01L21/28097 ,  H01L21/3215 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/66507

摘要： A method of manufacturing a semiconductor device having a MOSFET of a first conductivity type and a MOSFET of a second conductivity type different from the first conductivity type formed on a semiconductor substrate, the method has: forming a gate insulating film; forming a first gate electrode layer, and forming a second gate electrode layer; forming a first metal containing layer on said first gate electrode layer and said second gate electrode layer; forming a second metal containing layer for preventing diffusion of a metal on said first metal containing layer; forming a third metal containing layer on said second gate electrode layer from which said first metal containing layer and said second metal containing layer are selectively removed, the third metal containing layer having a thickness different from the thickness of said first metal containing layer in a case where the third metal containing layer contains the same metal or alloy as the metal or alloy contained in said first metal containing layer; and performing a thermal processing, thereby causing reaction between the metal contained in said first metal containing layer and said first gate electrode layer to convert said first gate electrode layer into an alloy and causing reaction between the metal contained in said third metal containing layer and said second gate electrode layer to convert said second gate electrode layer into an alloy, thereby forming gate electrodes of different compositions.

摘要翻译： 一种制造具有第一导电类型的MOSFET的半导体器件的方法和形成在半导体衬底上的与第一导电类型不同的第二导电类型的MOSFET，该方法具有：形成栅极绝缘膜; 形成第一栅电极层，形成第二栅电极层; 在所述第一栅电极层和所述第二栅电极层上形成第一含金属层; 形成用于防止金属在所述第一金属含有层上的扩散的第二含金属层; 在所述第二栅电极层上形成第三金属含有层，从所述第二金属含有层和所述第二金属含有层选择性地除去所述第三金属含有层，所述第三金属含有层的厚度与所述第一金属含有层的厚度不同 其中所述第三含金属层包含与所述第一含金属层中所含的金属或合金相同的金属或合金; 并进行热处理，从而使包含在所述第一金属含有层中的金属与所述第一栅极电极层之间产生反应，将所述第一栅电极层转换成合金，并引起所述第三金属含有层中含有的金属与所述 第二栅极电极层，以将所述第二栅电极层转换成合金，从而形成不同组成的栅极。

公开(公告)号：US20070278587A1

公开(公告)日：2007-12-06

申请号：US11798068

申请日：2007-05-10

申请人： Tomonori Aoyama ,  Tomohiro Saito ,  Katsuyuki Sekine ,  Kazuaki Nakajima ,  Motoyuki Sato ,  Takuya Kobayashi

发明人： Tomonori Aoyama ,  Tomohiro Saito ,  Katsuyuki Sekine ,  Kazuaki Nakajima ,  Motoyuki Sato ,  Takuya Kobayashi

IPC分类号： H01L29/94

CPC分类号： H01L21/26513 ,  H01L21/26506 ,  H01L21/28079 ,  H01L21/28097 ,  H01L21/28202 ,  H01L21/2822 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/785

摘要： This disclosure concerns a semiconductor device comprising a semiconductor substrate; a gate dielectric film provided on the semiconductor substrate and containing Hf, Si, and O or containing Zr, Si and O; a gate electrode of an n-channel FET provided on the gate dielectric film, the gate electrode being made of nickel silicide containing nickel at a higher content than silicon; an aluminum layer provided at a bottom portion of the gate electrode of the n-channel FET; and a gate electrode of a p-channel FET provided on the gate dielectric film, the gate electrode being made of nickel silicide containing nickel at a higher content than silicon.

摘要翻译： 本公开涉及包括半导体衬底的半导体器件; 设置在半导体衬底上并含有Hf，Si和O或含有Zr，Si和O的栅极电介质膜; 设置在所述栅极电介质膜上的n沟道FET的栅电极，所述栅电极由含有比所述硅含量高的镍的镍硅化物制成; 设置在n沟道FET的栅电极的底部的铝层; 以及设置在所述栅极电介质膜上的p沟道FET的栅电极，所述栅电极由镍含量高于硅的镍的硅化镍制成。

公开(公告)号：US20060273413A1

公开(公告)日：2006-12-07

申请号：US11185678

申请日：2005-07-21

申请人： Motoyuki Sato ,  Katsuyuki Sekine ,  Kazuaki Nakajima ,  Tomohiro Saito ,  Kazuhiro Eguchi ,  Atsushi Yagishita

发明人： Motoyuki Sato ,  Katsuyuki Sekine ,  Kazuaki Nakajima ,  Tomohiro Saito ,  Kazuhiro Eguchi ,  Atsushi Yagishita

IPC分类号： H01L29/94

CPC分类号： H01L21/823462 ,  H01L21/82345 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

摘要： There are provided: a semiconductor substrate including first and second device regions isolated by device isolation regions; a first gate insulating film of a high-k material formed in the first device region; a first gate electrode formed on the first gate insulating film; first source and drain regions formed at both sides of the first gate electrode in the first device region; a second gate insulating film of a high-k material which is different from the high-k material of the first gate insulating film, the second gate insulating film being formed in the second device region; a second gate electrode formed on the second gate insulating film; and second source and drain regions formed at both sides of the second gate electrode in the second device region.

摘要翻译： 提供：包括由器件隔离区域隔离的第一和第二器件区域的半导体衬底; 形成在所述第一器件区域中的高k材料的第一栅极绝缘膜; 形成在第一栅极绝缘膜上的第一栅电极; 形成在第一器件区域中的第一栅电极的两侧的第一源极和漏极区; 与所述第一栅极绝缘膜的高k材料不同的高k材料的第二栅极绝缘膜，所述第二栅极绝缘膜形成在所述第二器件区域中; 形成在所述第二栅极绝缘膜上的第二栅电极; 以及形成在第二器件区域中的第二栅电极的两侧的第二源极和漏极区。

公开(公告)号：US20100003813A1

公开(公告)日：2010-01-07

申请号：US12585334

申请日：2009-09-11

申请人： Katsuyuki Sekine ,  Akio Kaneko ,  Motoyuki Sato ,  Seiji Inumiya ,  Kazuhiro Eguchi

发明人： Katsuyuki Sekine ,  Akio Kaneko ,  Motoyuki Sato ,  Seiji Inumiya ,  Kazuhiro Eguchi

IPC分类号： H01L21/28

CPC分类号： C23C16/401 ,  C23C16/56 ,  H01L21/02329 ,  H01L21/3145

摘要： According to the present invention, there is provided a semiconductor device comprising: a gate insulating film selectively formed on a predetermined region of a semiconductor substrate; a gate electrode formed on said gate insulating film; and a source region and drain region formed, in a surface portion of said semiconductor substrate, on two sides of a channel region positioned below said gate electrode, wherein a carbon concentration in an interface where said gate insulating film is in contact with said gate electrode is not more than 5×1022 atoms/cm3.

摘要翻译： 根据本发明，提供了一种半导体器件，包括：选择性地形成在半导体衬底的预定区域上的栅极绝缘膜; 形成在所述栅极绝缘膜上的栅电极; 以及在所述半导体衬底的表面部分中形成在位于所述栅极电极下方的沟道区域的两侧上的源极区和漏极区，其中所述栅极绝缘膜与所述栅电极接触的界面中的碳浓度 不大于5×1022原子/ cm3。

公开(公告)号：US07687869B2

公开(公告)日：2010-03-30

申请号：US12081824

申请日：2008-04-22

申请人： Akio Kaneko ,  Seiji Inumiya ,  Katsuyuki Sekine ,  Kazuhiro Eguchi ,  Motoyuki Sato

发明人： Akio Kaneko ,  Seiji Inumiya ,  Katsuyuki Sekine ,  Kazuhiro Eguchi ,  Motoyuki Sato

IPC分类号： H01L29/78 ,  H01L21/8238

CPC分类号： H01L21/28194 ,  H01L21/28079 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/513 ,  H01L29/517 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device according to the present invention comprises a semiconductor substrate, a gate insulating film which is composed of a material whose main component is a tetravalent metal oxide, a mixture of a tetravalent metal oxide and SiO2, or a mixture of a tetravalent metal oxide and SiON and which containing B when it is in an nMOS structure on the semiconductor substrate or containing at least one of P and As when it is in a pMOS structure on the semiconductor substrate, and a gate electrode made of a metal having a work function of 4 eV to 5.5 eV.

摘要翻译： 根据本发明的半导体器件包括半导体衬底，由主要成分为四价金属氧化物的材料，四价金属氧化物和SiO 2的混合物或四价金属氧化物的混合物构成的栅极绝缘膜 和SiON，并且当其在半导体衬底上处于pMOS结构中时在半导体衬底上为nMOS结构或含有P和As中的至少一种时含有B，并且由具有功函数的金属制成的栅电极 4 eV至5.5 eV。

公开(公告)号：US20050110101A1

公开(公告)日：2005-05-26

申请号：US10927115

申请日：2004-08-27

申请人： Akio Kaneko ,  Kazuhiro Eguchi ,  Seiji Inumiya ,  Katsuyuki Sekine ,  Motoyuki Sato

发明人： Akio Kaneko ,  Kazuhiro Eguchi ,  Seiji Inumiya ,  Katsuyuki Sekine ,  Motoyuki Sato

IPC分类号： C23C14/10 ,  C23C16/42 ,  H01L21/28 ,  H01L21/316 ,  H01L21/336 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/04 ,  H01L27/08 ,  H01L27/088 ,  H01L27/092 ,  H01L27/115 ,  H01L27/12 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L29/786 ,  H01L29/76

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28211 ,  H01L27/115 ,  H01L27/1203 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66825 ,  H01L29/78

摘要： A semiconductor apparatus wherein a device formed on a semiconductor substrate comprises a gate insulating film including a high dielectric constant film formed on the substrate and an anti-reaction film formed on the high dielectric constant film, and a gate electrode formed on the anti-reaction film, the high dielectric constant film comprises a film containing at least one of Hf and Zr, and Si and O, or a film containing at least one of Hf and Zr, and Si, O and N, the anti-reaction film comprises an SiO2 film, a film containing SiO2 as a main component and at least one of Hf and Zr, a film containing SiO2 as a main component and N, a film containing SiO2 as a main component, Hf and N, a film containing SiO2 as a main component, Zr and N, or a film containing SiO2 as a main component, Hf, Zr and N.

摘要翻译： 一种半导体装置，其中形成在半导体衬底上的器件包括栅极绝缘膜，该栅极绝缘膜包括形成在基底上的高介电常数膜和形成在高介电常数膜上的抗反应膜，以及形成在抗反应上的栅电极 高介电常数膜包括含有Hf和Zr中的至少一种以及Si和O的膜，或包含Hf和Zr中的至少一种以及Si，O和N的膜，所述抗反应膜包括 SiO 2膜，含有SiO 2作为主要成分的膜和Hf和Zr中的至少一种的膜，含有SiO 2的膜作为 主要成分为N，以SiO 2为主要成分的膜，Hf和N，以SiO 2为主要成分的膜，Zr和N，或膜 含有SiO 2作为主要成分的Hf，Zr和N.

公开(公告)号：US20050067704A1

公开(公告)日：2005-03-31

申请号：US10738049

申请日：2003-12-18

申请人： Akio Kaneko ,  Seiji Inumiya ,  Katsuyuki Sekine ,  Kazuhiro Eguchi ,  Motoyuki Sato

发明人： Akio Kaneko ,  Seiji Inumiya ,  Katsuyuki Sekine ,  Kazuhiro Eguchi ,  Motoyuki Sato

IPC分类号： H01L21/283 ,  H01L21/28 ,  H01L21/316 ,  H01L21/336 ,  H01L21/8238 ,  H01L23/48 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78

CPC分类号： H01L21/28194 ,  H01L21/28079 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/513 ,  H01L29/517 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device according to the present invention comprises a semiconductor substrate, a gate insulating film which is composed of a material whose main component is a tetravalent metal oxide, a mixture of a tetravalent metal oxide and SiO2, or a mixture of a tetravalent metal oxide and SiON and which containing B when it is in an nMOS structure on the semiconductor substrate or containing at least one of P and As when it is in a pMOS structure on the semiconductor substrate, and a gate electrode made of a metal having a work function of 4 eV to 5.5 eV.

摘要翻译： 根据本发明的半导体器件包括半导体衬底，由主要成分为四价金属氧化物的材料，四价金属氧化物和SiO 2的混合物或四价金属氧化物的混合物构成的栅极绝缘膜 和SiON，并且当其在半导体衬底上处于pMOS结构中时在半导体衬底上为nMOS结构或含有P和As中的至少一种时含有B，并且由具有功函数的金属制成的栅电极 4 eV至5.5 eV。

公开(公告)号：US20100173487A1

公开(公告)日：2010-07-08

申请号：US12654559

申请日：2009-12-23

申请人： Akio Kaneko ,  Kazuhiro Eguchi ,  Seiji Inumiya ,  Katsuyuki Sekine ,  Motoyuki Sato

发明人： Akio Kaneko ,  Kazuhiro Eguchi ,  Seiji Inumiya ,  Katsuyuki Sekine ,  Motoyuki Sato

IPC分类号： H01L21/28

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28211 ,  H01L27/115 ,  H01L27/1203 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66825 ,  H01L29/78

摘要： A semiconductor apparatus wherein a device formed on a semiconductor substrate comprises a gate insulating film including a high dielectric constant film formed on the substrate and an anti-reaction film formed on the high dielectric constant film, and a gate electrode formed on the anti-reaction film, the high dielectric constant film comprises a film containing at least one of Hf and Zr, and Si and O, or a film containing at least one of Hf and Zr, and Si, O and N, the anti-reaction film comprises an SiO2 film, a film containing SiO2 as a main component and at least one of Hf and Zr, a film containing SiO2 as a main component and N, a film containing SiO2 as a main component, Hf and N, a film containing SiO2 as a main component, Zr and N, or a film containing SiO2 as a main component, Hf, Zr and N.

公开(公告)号：US20100159686A1

公开(公告)日：2010-06-24

申请号：US12659250

申请日：2010-03-02

申请人： Akio Kaneko ,  Seiji Inumiya ,  Katsuyuki Sekine ,  Kazuhiro Eguchi ,  Motoyuki Sato

发明人： Akio Kaneko ,  Seiji Inumiya ,  Katsuyuki Sekine ,  Kazuhiro Eguchi ,  Motoyuki Sato

IPC分类号： H01L21/28

CPC分类号： H01L21/28194 ,  H01L21/28079 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/513 ,  H01L29/517 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device according to the present invention comprises a semiconductor substrate, a gate insulating film which is composed of a material whose main component is a tetravalent metal oxide, a mixture of a tetravalent metal oxide and SiO2, or a mixture of a tetravalent metal oxide and SiON and which containing B when it is in an nMOS structure on the semiconductor substrate or containing at least one of P and As when it is in a pMOS structure on the semiconductor substrate, and a gate electrode made of a metal having a work function of 4 eV to 5.5 eV.