公开(公告)号：US08541768B2

公开(公告)日：2013-09-24

申请号：US13118402

申请日：2011-05-28

申请人： Akio Shima ,  Yoshitska Sasago ,  Toshiyuki Mine ,  Masaharu Kinoshita

发明人： Akio Shima ,  Yoshitska Sasago ,  Toshiyuki Mine ,  Masaharu Kinoshita

IPC分类号： H01L29/02

CPC分类号： H01L27/2454 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675 ,  H01L45/1683

摘要： A technique used for a semiconductor device formed by stacking multiple structural bodies each having a semiconductor device, for preventing generation of thermal load on a structural body at a lower layer which is caused by a laser used in a step of forming a structural body at an upper layer. In a phase-change memory including multiple stacked memory matrices, a metal film is disposed between a memory matrix at a lower layer and a memory matrix at an upper layer formed over the memory matrix at the lower layer, in which the laser used for forming the memory matrix is reflected at the metal film and prevented from transmitting the metal film, thereby preventing the phase-change material layer, etc. in the memory matrix at the lower layer from being directly heated excessively by the laser.

摘要翻译： 一种用于半导体器件的技术，该半导体器件通过堆叠多个具有半导体器件的结构体而形成，用于防止由在用于形成结构体的步骤中使用的激光器引起的下层的结构体上的热负荷的产生 上层。 在包括多个堆叠的存储器矩阵的相变存储器中，金属膜设置在下层的存储矩阵和在下层的存储矩阵上形成的上层的存储矩阵之间，其中用于形成的激光 存储矩阵在金属膜处被反射并且防止金属膜透射，从而防止下层的存储矩阵中的相变材料层等被激光过度直接加热。

公开(公告)号：US08427865B2

公开(公告)日：2013-04-23

申请号：US13440225

申请日：2012-04-05

申请人： Akio Shima ,  Yoshitaka Sasago ,  Masaharu Kinoshita ,  Toshiyuki Mine ,  Norikatsu Takaura ,  Takahiro Morikawa ,  Kenzo Kurotsuchi ,  Satoru Hanzawa

发明人： Akio Shima ,  Yoshitaka Sasago ,  Masaharu Kinoshita ,  Toshiyuki Mine ,  Norikatsu Takaura ,  Takahiro Morikawa ,  Kenzo Kurotsuchi ,  Satoru Hanzawa

IPC分类号： G11C11/00 ,  H01L29/80

CPC分类号： H01L27/2481 ,  G11C13/0004 ,  G11C13/003 ,  G11C2213/71 ,  G11C2213/75 ,  G11C2213/79 ,  H01L27/2454 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1683

摘要： There is provided a semiconductor storage device which is capable of further reducing a size of a memory cell, and increasing a storage capacity. Plural memory cells each including a transistor formed on a semiconductor substrate, and a variable resistive device having a resistance value changed by voltage supply and connected between source and drain terminals of the transistor are arranged longitudinally and in an array to configure a three-dimensional memory cell array. A memory cell structure has a double channel structure in which an inside of a switching transistor is filled with a variable resistance element, particularly, a phase change material. The switching transistor is turned off by application of a voltage to increase a channel resistance so that a current flows in the internal phase change material to operate the memory.

摘要翻译： 提供了能够进一步减小存储单元的尺寸并增加存储容量的半导体存储装置。 每个包括形成在半导体衬底上的晶体管的多个存储单元以及具有由电压供应改变并连接在晶体管的源极和漏极端子之间的电阻值的可变电阻器件被纵向排列成阵列以构成三维存储器 单元格阵列。 存储单元结构具有双通道结构，其中开关晶体管的内部填充有可变电阻元件，特别是相变材料。 通过施加电压来切换开关晶体管，以增加沟道电阻，使得电流在内部相变材料中流动以操作存储器。

公开(公告)号：US20080145987A1

公开(公告)日：2008-06-19

申请号：US11943639

申请日：2007-11-21

申请人： Akio Shima

发明人： Akio Shima

IPC分类号： H01L21/336

CPC分类号： H01L21/823814 ,  H01L21/26513 ,  H01L21/268 ,  H01L21/8249 ,  H01L27/1052

摘要： A reflectance-controlling layer whose reflectance to irradiation of laser light becomes lower as a thickness thereof becomes thinner is formed on a semiconductor substrate having a first region and a second region. Thereafter, the reflectance-controlling layer on the first region is etched. Then, a laser light is irradiated to the semiconductor substrate to anneal an n−-type semiconductor region and an n+-type semiconductor region of the first region. In the same manner, after the reflectance-controlling layer is formed on the semiconductor substrate, the reflectance-controlling layer on the second region is etched. Then, a laser light is irradiated to the semiconductor substrate to anneal a p−-type semiconductor region and a p+-type semiconductor region of the second region.

摘要翻译： 在具有第一区域和第二区域的半导体衬底上形成反射率控制层，其反射率随着其厚度变薄而变低。 此后，蚀刻第一区域上的反射率控制层。 然后，将激光照射到半导体衬底上，以退火第一区域的n + O - 型半导体区域和n + + + / - 半导体区域。 以相同的方式，在半导体衬底上形成反射控制层之后，蚀刻第二区域上的反射控制层。 然后，将激光照射到半导体衬底上，以退火第二区域的p + / - 型半导体区域和p + + + / - 半导体区域。

公开(公告)号：US07174735B2

公开(公告)日：2007-02-13

申请号：US10764374

申请日：2004-01-22

申请人： Kouichi Satoh ,  Seiji Yanagisawa ,  Shu Watabe ,  Yukihiro Fujita ,  Akio Shima ,  Yuji Tanaka ,  Shinichi Takahashi ,  Hiroshi Kunii

发明人： Kouichi Satoh ,  Seiji Yanagisawa ,  Shu Watabe ,  Yukihiro Fujita ,  Akio Shima ,  Yuji Tanaka ,  Shinichi Takahashi ,  Hiroshi Kunii

IPC分类号： F25B27/00 ,  G05D23/00

CPC分类号： F24F5/0017 ,  Y02E10/22 ,  Y02E10/28 ,  Y02E60/147 ,  Y02E60/17 ,  Y02P70/525

摘要： In the air-conditioning system, a primary side to generate heat includes a heat storage and a heat source and produces cool or warm water using an inexpensive commercial power source such as a nighttime power source. A system collaboration unit is disposed between a motor to drive a water pump and a power source. The unit is connected to the motor via a cable. An output from the inverter is connected to the motor via a cable.

公开(公告)号：US20130228739A1

公开(公告)日：2013-09-05

申请号：US13884263

申请日：2010-12-06

申请人： Yoshitaka Sasago ,  Masaharu Kinoshita ,  Mitsuharu Tai ,  Akio Shima ,  Kenzo Kurotsuchi ,  Takashi Kobayashi

发明人： Yoshitaka Sasago ,  Masaharu Kinoshita ,  Mitsuharu Tai ,  Akio Shima ,  Kenzo Kurotsuchi ,  Takashi Kobayashi

IPC分类号： H01L45/00

CPC分类号： H01L45/1608 ,  G11C13/0004 ,  G11C2213/75 ,  H01L27/0688 ,  H01L27/1021 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/2409 ,  H01L27/2454 ,  H01L27/2481 ,  H01L27/249 ,  H01L29/7926 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1675

摘要： When a thin channel semiconductor layer formed on a side wall of a stacked film in which insulating films and gate electrodes are alternately stacked together is removed on the stacked film, a contact resistance between a vertical transistor including the channel semiconductor layer and the gate electrode, and a bit line formed on the stacked film is prevented from rising. As its means, a conductive layer electrically connected to the channel semiconductor layer is disposed immediately above the stacked film.

摘要翻译： 当在叠层薄膜上除去形成在绝缘膜和栅电极交替层叠在一起的叠层膜的侧壁上的薄沟道半导体层时，包括沟道半导体层的垂直晶体管与栅电极之间的接触电阻， 并且防止形成在层叠膜上的位线上升。 作为其手段，电连接到沟道半导体层的导电层设置在堆叠膜的正上方。

公开(公告)号：US20090085042A1

公开(公告)日：2009-04-02

申请号：US12219837

申请日：2008-07-29

申请人： Toshiyuki Mine ,  Mitsuharu Tai ,  Akio Shima

发明人： Toshiyuki Mine ,  Mitsuharu Tai ,  Akio Shima

IPC分类号： H01L21/20 ,  H01L29/04

CPC分类号： H01L21/268 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/02675 ,  H01L21/02686 ,  H01L27/1285 ,  H01L29/78642

摘要： A display device having a thin film semiconductor device including a semiconductor thin film having first and second semiconductor regions formed each into a predetermined shape above an insulative substrate, a conductor fabricated into a predetermined shape to the semiconductor thin film and a dielectric film put between the semiconductor thin film and the conductor, in which the semiconductor thin film is a polycrystal thin film with the crystallization ratio thereof exceeding 90% and the difference of unevenness on the surface of the semiconductor thin film does not exceed 10 nm.

摘要翻译： 一种具有薄膜半导体器件的显示装置，该薄膜半导体器件包括半导体薄膜，该半导体薄膜具有在绝缘性基板的上方形成为规定形状的第一半导体区域和第二半导体区域，对该半导体薄膜形成为规定形状的导体， 半导体薄膜和导体，其中半导体薄膜是结晶比率超过90％的多晶薄膜，并且半导体薄膜的表面上的不均匀度不超过10nm。

公开(公告)号：US07098111B2

公开(公告)日：2006-08-29

申请号：US10948142

申请日：2004-09-24

申请人： Akio Shima

发明人： Akio Shima

IPC分类号： H01L21/336

CPC分类号： H01L21/8249 ,  H01L21/823814

摘要： A manufacturing technology of a MOSFET having a shallow junction and a source and drain of a low resistance is provided. After having ion-implanted an As on the surface of a p type well forming a gate electrode, a surface protection layer and an energy absorber layer are deposited on a substrate. When the surface of the substrate is irradiated by a YAG laser beam of the wavelength of 1064 nm for one nano second to 999 nano seconds, a heat absorbed by the energy absorber layer is transmitted to the substrate in an ultra short time, and heats its surface to a melting temperature, and therefore, the impurity is activated, and an extension region of a low resistance is formed in an extremely shallow region of about 20 nm in depth from the surface of the p type well.

摘要翻译： 提供具有浅结的MOSFET和低电阻的源极和漏极的制造技术。 在形成栅电极的p型阱的表面上离子注入As之后，在基板上沉积表面保护层和能量吸收层。 当衬底的表面被波长为1064nm的YAG激光束照射一纳秒至999纳秒时，能量吸收层吸收的热量在极短的时间内被传送到衬底上，并将其加热 表面到熔融温度，因此杂质被激活，并且从p型阱的表面开始深度约20nm的极浅的区域形成低电阻的延伸区域。

公开(公告)号：US08866123B2

公开(公告)日：2014-10-21

申请号：US13884331

申请日：2010-11-22

申请人： Yoshitaka Sasago ,  Masaharu Kinoshita ,  Takahiro Morikawa ,  Akio Shima ,  Takashi Kobayashi

发明人： Yoshitaka Sasago ,  Masaharu Kinoshita ,  Takahiro Morikawa ,  Akio Shima ,  Takashi Kobayashi

IPC分类号： H01L47/00 ,  H01L45/00 ,  H01L29/792 ,  H01L27/24 ,  H01L29/66 ,  H01L27/115

CPC分类号： H01L27/2436 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/2409 ,  H01L27/2454 ,  H01L27/2481 ,  H01L27/249 ,  H01L29/66833 ,  H01L29/7926 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1616 ,  H01L45/1683

摘要： A vertical chain memory includes two-layer select transistors having first select transistors which are vertical transistors arranged in a matrix, and second select transistors which are vertical transistors formed on the respective first select transistors, and a plurality of memory cells connected in series on the two-layer select transistors. With this configuration, the adjacent select transistors are prevented from being selected by respective shared gates, the plurality of two-layer select transistors can be selected, independently, and a storage capacity of a non-volatile storage device is prevented from being reduced.

摘要翻译： 垂直链式存储器包括具有第一选择晶体管的两层选择晶体管，它们是以矩阵形式排列的垂直晶体管，第二选择晶体管是形成在各个第一选择晶体管上的垂直晶体管，以及多个存储单元串联连接 双层选择晶体管。 利用这种配置，防止相邻的选择晶体管被相应的共享栅极选择，可以独立地选择多个两层选择晶体管，并且防止非易失性存储装置的存储容量减小。

公开(公告)号：US20130341729A1

公开(公告)日：2013-12-26

申请号：US13812181

申请日：2011-06-20

申请人： Digh Hisamoto ,  Shinichi Saito ,  Akio Shima ,  Hiroyuki Yoshimoto

发明人： Digh Hisamoto ,  Shinichi Saito ,  Akio Shima ,  Hiroyuki Yoshimoto

IPC分类号： H01L27/06

CPC分类号： H01L27/1203 ,  G11C11/412 ,  G11C16/0408 ,  H01L21/8249 ,  H01L21/84 ,  H01L23/535 ,  H01L27/0623 ,  H01L27/0705 ,  H01L27/092 ,  H01L27/1025 ,  H01L27/1026 ,  H01L27/11 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/0847 ,  H01L29/0895 ,  H01L29/1004 ,  H01L29/1033 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7311 ,  H01L29/788 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is a semiconductor element having, while maintaining the same integratability as a conventional MOSFET, excellent switch characteristics compared with the MOSFET, that is, having the S-value less than 60 mV/order at room temperature. Combining the MOSFET and a tunnel bipolar transistor having a tunnel junction configures a semiconductor element that shows an abrupt change in the drain current with respect to a change in the gate voltage (an S-value of less than 60 mV/order) even at a low voltage.

摘要翻译： 提供了与MOSFET相比具有与常规MOSFET相同的可集成性的半导体元件，即在室温下S值小于60mV /阶的优异的开关特性。 组合MOSFET和具有隧道结的隧道双极晶体管配置了一个半导体元件，其相对于栅极电压的变化（S值小于60mV /次）显示出漏极电流的突然变化，即使在 低电压。

公开(公告)号：US07906834B2

公开(公告)日：2011-03-15

申请号：US12219837

申请日：2008-07-29

申请人： Toshiyuki Mine ,  Mitsuharu Tai ,  Akio Shima

发明人： Toshiyuki Mine ,  Mitsuharu Tai ,  Akio Shima

IPC分类号： H01L23/552

CPC分类号： H01L21/268 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/02675 ,  H01L21/02686 ,  H01L27/1285 ,  H01L29/78642

摘要： A display device having a thin film semiconductor device including a semiconductor thin film having first and second semiconductor regions formed each into a predetermined shape above an insulative substrate, a conductor fabricated into a predetermined shape to the semiconductor thin film and a dielectric film put between the semiconductor thin film and the conductor, in which the semiconductor thin film is a polycrystal thin film with the crystallization ratio thereof exceeding 90% and the difference of unevenness on the surface of the semiconductor thin film does not exceed 10 nm.

摘要翻译： 一种具有薄膜半导体器件的显示装置，该薄膜半导体器件包括半导体薄膜，该半导体薄膜具有在绝缘性基板的上方形成为规定形状的第一半导体区域和第二半导体区域，对该半导体薄膜形成为规定形状的导体， 半导体薄膜和导体，其中半导体薄膜是结晶比率超过90％的多晶薄膜，并且半导体薄膜的表面上的不均匀度不超过10nm。