公开(公告)号：US06238626B1

公开(公告)日：2001-05-29

申请号：US09289607

申请日：1999-04-12

申请人： Akira Higuchi ,  Eiji Watanabe ,  Naoki Miyazaki ,  Kanji Yahiro ,  Kenichi Kuroda ,  Hideyoshi Kitahara ,  Kenji Ishiyama ,  Takashi Daikoku

发明人： Akira Higuchi ,  Eiji Watanabe ,  Naoki Miyazaki ,  Kanji Yahiro ,  Kenichi Kuroda ,  Hideyoshi Kitahara ,  Kenji Ishiyama ,  Takashi Daikoku

IPC分类号： B01L302

CPC分类号： G01N35/10 ,  B01L3/0275 ,  G01N2035/103 ,  Y10T436/2575

摘要： In a method for distributing liquids, in which a distribution tip attached detachably to the lower end of a distribution nozzle can be replaced at any time necessary, a tip rack having a plurality of unused distribution tips lined up thereon is placed on a fitting stage to have the distribution tips fitted with a distribution nozzles. Then, the existence, or non-existence, of a distribution tip left behind on the tip rack without being attached to a distribution nozzle after the fitting operation is finished is detected by a detection section formed of an interrupting-type light sensor, the targeted place of detection by the light sensor being the lower end of the distribution tip. Under the above-described structure, misfitting of a distribution tip can be detected with a high certainty at an early stage before an operation for sucking/discharging liquids is started.

摘要翻译： 在分配液体的方法中，可以随时更换可分配到分配喷嘴的下端的分配末端，其中具有多个未分配的未分配尖端的末端齿条放置在装配台上 具有配有分配喷嘴的分配头。 然后，通过由中断型光传感器形成的检测部分来检测在装配操作完成后未附着在分配喷嘴上的尖端齿条上留下的分配尖端的存在或不存在，目标 光传感器的检测位置是分配尖端的下端。 在上述结构之前，可以在开始吸取/排出液体的操作之前的早期阶段高精度地检测分配尖端的错配。

公开(公告)号：US06299840B1

公开(公告)日：2001-10-09

申请号：US09281223

申请日：1999-03-30

申请人： Eiji Watanabe ,  Kanji Yahiro ,  Akira Higuchi ,  Naoki Miyazaki ,  Kenichi Kuroda ,  Kenji Ishiyama ,  Takashi Daikoku ,  Hideyoshi Kitahara

发明人： Eiji Watanabe ,  Kanji Yahiro ,  Akira Higuchi ,  Naoki Miyazaki ,  Kenichi Kuroda ,  Kenji Ishiyama ,  Takashi Daikoku ,  Hideyoshi Kitahara

IPC分类号： G01N2100

CPC分类号： G01N35/0099 ,  G01N35/028 ,  G01N35/1074 ,  G01N2035/00356 ,  G01N2035/0425 ,  G01N2035/0498

摘要： In an automatic testing apparatus comprising, a specimen holder area adapted to hold thereon a specimen substrate for receiving therein a specimen, a reagent injector adapted to inject a reagent toward the specimen in the specimen substrate on the specimen holder area to mix the specimen with the reagent, a mixture reaction device adapted to hold thereon the specimen substrate including the mixture of the specimen and the reagent within a predetermined circumferential condition during a time period, and a transferring device for transferring the specimen substrate relative to the specimen holder area, the mixture reaction device has a take-in area to which the specimen substrate is transferred from the specimen holder area by the transferring device, and the take-in area is arranged adjacent to the specimen holder area.

摘要翻译： 一种自动检测装置，其特征在于，包括：试样保持区域，其适于在其上容纳有用于容纳试样的试样基板，适于向试样保持体区域的试样基板上的试样注入试剂，将试样与 试剂，混合反应装置，其适于在一段时间内在预定的周向状态下将包含试样和试剂的混合物的试样基板保持在其上，以及用于相对于试样保持器区域传送试样基板的转印装置， 反应装置具有通过转印装置从试样保持体区域将试样基板从其移送到的入口区域，并且导入区域邻近试样保持器区域布置。

公开(公告)号：US09059193B2

公开(公告)日：2015-06-16

申请号：US13514201

申请日：2010-12-27

申请人： Kenichi Ohtsuka ,  Kenichi Kuroda ,  Hiroshi Watanabe ,  Naoki Yutani ,  Hiroaki Sumitani

发明人： Kenichi Ohtsuka ,  Kenichi Kuroda ,  Hiroshi Watanabe ,  Naoki Yutani ,  Hiroaki Sumitani

IPC分类号： H01L29/15 ,  H01L29/66 ,  C30B23/02 ,  C30B25/02 ,  C30B29/36 ,  H01L21/02 ,  H01L29/10 ,  H01L29/16 ,  H01L29/872 ,  H01L21/04 ,  H01L29/78

CPC分类号： H01L29/66068 ,  C30B23/02 ,  C30B25/02 ,  C30B29/36 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/02447 ,  H01L21/02496 ,  H01L21/02529 ,  H01L21/02576 ,  H01L21/0495 ,  H01L29/107 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/7802 ,  H01L29/7827 ,  H01L29/872

摘要： A silicon carbide semiconductor element, including: i) an n-type silicon carbide substrate doped with a dopant, such as nitrogen, at a concentration C, wherein the substrate has a lattice constant that decreases with doping; ii) an n-type silicon carbide epitaxially-grown layer doped with the dopant, but at a smaller concentration than the substrate; and iii) an n-type buffer layer doped with the dopant, and arranged between the substrate and the epitaxially-grown layer, wherein the buffer layer has a multilayer structure in which two or more layers having the same thickness are laminated, and is configured such that, based on a number of layers (N) in the multilayer structure, a doping concentration of a K-th layer from a silicon carbide epitaxially-grown layer side is C·K/(N+1).

摘要翻译： 一种碳化硅半导体元件，包括：i）以浓度C掺杂有诸如氮的掺杂剂的n型碳化硅衬底，其中所述衬底具有随着掺杂而降低的晶格常数; ii）掺杂有掺杂剂但以比衬底更小的浓度的n型碳化硅外延生长层; 并且iii）掺杂有掺杂剂的n型缓冲层，并且布置在所述衬底和所述外延生长层之间，其中所述缓冲层具有其中层叠具有相同厚度的两层或更多层的多层结构，并且被配置 使得基于多层结构中的多个层（N），来自碳化硅外延生长层的第K层的掺杂浓度为C·K /（N + 1）。

公开(公告)号：US08569123B2

公开(公告)日：2013-10-29

申请号：US13258941

申请日：2009-09-01

申请人： Yoshinori Matsuno ,  Kenichi Ohtsuka ,  Naoki Yutani ,  Kenichi Kuroda ,  Hiroshi Watanabe ,  Shozo Shikama

发明人： Yoshinori Matsuno ,  Kenichi Ohtsuka ,  Naoki Yutani ,  Kenichi Kuroda ,  Hiroshi Watanabe ,  Shozo Shikama

IPC分类号： H01L21/338

CPC分类号： H01L21/046 ,  H01L21/0495 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/872

摘要： An object is to provide a method for manufacturing a silicon carbide semiconductor device in which a time required for removing a sacrificial oxide film can be shortened and damage to a surface of the silicon carbide layer can be reduced. The method for manufacturing a silicon carbide semiconductor device includes: (a) performing ion implantation to a silicon carbide layer; (b) performing activation annealing to the ion-implanted silicon carbide layer 2; (c) removing a surface layer of the silicon carbide layer 2, to which the activation annealing has been performed, by dry etching; (d) forming a sacrificial oxide film on a surface layer of the silicon carbide layer, to which the dry etching has been performed, by performing sacrificial oxidation thereto; and (e) removing the sacrificial oxide film by wet etching.

摘要翻译： 本发明的目的是提供一种用于制造碳化硅半导体器件的方法，其中可以缩短去除牺牲氧化膜所需的时间，并且可以降低对碳化硅层的表面的损坏。 制造碳化硅半导体器件的方法包括：（a）对碳化硅层进行离子注入; （b）对离子注入碳化硅层2进行激活退火; （c）通过干蚀刻去除已经进行了活化退火的碳化硅层2的表面层; （d）通过对其进行牺牲氧化，在已经进行了干蚀刻的碳化硅层的表面层上形成牺牲氧化膜; 和（e）通过湿蚀刻去除牺牲氧化膜。

公开(公告)号：US20120241766A1

公开(公告)日：2012-09-27

申请号：US13514201

申请日：2010-12-27

申请人： Kenichi Ohtsuka ,  Kenichi Kuroda ,  Hiroshi Watanabe ,  Naoki Yutani ,  Hiroaki Sumitani

发明人： Kenichi Ohtsuka ,  Kenichi Kuroda ,  Hiroshi Watanabe ,  Naoki Yutani ,  Hiroaki Sumitani

IPC分类号： H01L29/167

CPC分类号： H01L29/66068 ,  C30B23/02 ,  C30B25/02 ,  C30B29/36 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/02447 ,  H01L21/02496 ,  H01L21/02529 ,  H01L21/02576 ,  H01L21/0495 ,  H01L29/107 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/7802 ,  H01L29/7827 ,  H01L29/872

摘要： A silicon carbide semiconductor element, including: i) an n-type silicon carbide substrate doped with a dopant, such as nitrogen, at a concentration C, wherein the substrate has a lattice constant that decreases with doping; ii) an n-type silicon carbide epitaxially-grown layer doped with the dopant, but at a smaller concentration than the substrate; and iii) an n-type buffer layer doped with the dopant, and arranged between the substrate and the epitaxially-grown layer, wherein the buffer layer has a multilayer structure in which two or more layers having the same thickness are laminated, and is configured such that, based on a number of layers (N) in the multilayer structure, a doping concentration of a K-th layer from a silicon carbide epitaxially-grown layer side is C·K/(N+1).

摘要翻译： 一种碳化硅半导体元件，包括：i）以浓度C掺杂有诸如氮的掺杂剂的n型碳化硅衬底，其中所述衬底具有随着掺杂而降低的晶格常数; ii）掺杂有掺杂剂但以比衬底更小的浓度的n型碳化硅外延生长层; 并且iii）掺杂有掺杂剂的n型缓冲层，并且布置在所述衬底和所述外延生长层之间，其中所述缓冲层具有其中层叠具有相同厚度的两层或更多层的多层结构，并且被配置 使得基于多层结构中的多个层（N），来自碳化硅外延生长层的第K层的掺杂浓度为C·K /（N + 1）。

公开(公告)号：US08119495B2

公开(公告)日：2012-02-21

申请号：US13096246

申请日：2011-04-28

申请人： Kenichi Kuroda ,  Kozo Watanabe ,  Hirohiko Yamamoto

发明人： Kenichi Kuroda ,  Kozo Watanabe ,  Hirohiko Yamamoto

IPC分类号： H01L21/76

CPC分类号： H01L23/5283 ,  H01L21/31053 ,  H01L21/74 ,  H01L21/76224 ,  H01L21/76229 ,  H01L23/522 ,  H01L23/528 ,  H01L23/53228 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/4925 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.

摘要翻译： 提供了一种用于改善嵌入在多个凹部中的构件的表面处的平坦度而不导致制造过程所需时间增加的技术。 根据该技术，通过将相对较宽区域的第一伪图案DP1和相对较小面积的第二虚设图案DP2放置在元件形成区域DA和虚拟区域FA之间的边界BL附近的虚拟图案， 在虚拟区域FA中。 由此，可以在虚拟区域FA的整个部分改善嵌入在隔离槽内的氧化硅膜的表面的平坦度。 此外，当第一伪图案DP1占据虚拟区域FA中相对较宽的区域时，可以控制掩模数据的增加。

公开(公告)号：US07948086B2

公开(公告)日：2011-05-24

申请号：US12714596

申请日：2010-03-01

申请人： Kenichi Kuroda ,  Kozo Watanabe ,  Hirohiko Yamamoto

发明人： Kenichi Kuroda ,  Kozo Watanabe ,  Hirohiko Yamamoto

IPC分类号： H01L23/48

CPC分类号： H01L23/5283 ,  H01L21/31053 ,  H01L21/74 ,  H01L21/76224 ,  H01L21/76229 ,  H01L23/522 ,  H01L23/528 ,  H01L23/53228 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/4925 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.

摘要翻译： 提供了一种用于改善嵌入在多个凹部中的构件的表面处的平坦度而不导致制造过程所需时间增加的技术。 根据该技术，通过将相对较宽区域的第一伪图案DP1和相对较小面积的第二虚设图案DP2放置在元件形成区域DA和虚拟区域FA之间的边界BL附近的虚拟图案， 在虚拟区域FA中。 由此，可以在虚拟区域FA的整个部分改善嵌入在隔离槽内的氧化硅膜的表面的平坦度。 此外，当第一伪图案DP1占据虚拟区域FA中相对较宽的区域时，可以控制掩模数据的增加。

公开(公告)号：US07589423B2

公开(公告)日：2009-09-15

申请号：US11802623

申请日：2007-05-24

申请人： Kenichi Kuroda ,  Kozo Watanabe ,  Hirohiko Yamamoto

发明人： Kenichi Kuroda ,  Kozo Watanabe ,  Hirohiko Yamamoto

IPC分类号： H01L23/48

CPC分类号： H01L23/5283 ,  H01L21/31053 ,  H01L21/74 ,  H01L21/76224 ,  H01L21/76229 ,  H01L23/522 ,  H01L23/528 ,  H01L23/53228 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/4925 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.

摘要翻译： 提供了一种用于改善嵌入在多个凹部中的构件的表面处的平坦度而不导致制造过程所需时间增加的技术。 根据该技术，通过将相对较宽区域的第一伪图案DP1和相对较小面积的第二虚设图案DP2放置在元件形成区域DA和虚拟区域FA之间的边界BL附近的虚拟图案， 在虚拟区域FA中。 由此，可以在虚拟区域FA的整个部分改善嵌入在隔离槽内的氧化硅膜的表面的平坦度。 此外，当第一伪图案DP1占据虚拟区域FA中相对较宽的区域时，可以控制掩模数据的增加。

公开(公告)号：US07411302B2

公开(公告)日：2008-08-12

申请号：US11430983

申请日：2006-05-10

申请人： Kenichi Kuroda ,  Kozo Watanabe ,  Hirohiko Yamamoto

发明人： Kenichi Kuroda ,  Kozo Watanabe ,  Hirohiko Yamamoto

IPC分类号： H01L23/48

CPC分类号： H01L23/5283 ,  H01L21/31053 ,  H01L21/74 ,  H01L21/76224 ,  H01L21/76229 ,  H01L23/522 ,  H01L23/528 ,  H01L23/53228 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/4925 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.

公开(公告)号：US20080028134A1

公开(公告)日：2008-01-31

申请号：US11860762

申请日：2007-09-25

申请人： Kiyoshi MATSUBARA ,  Naoki Yashiki ,  Shiro Baba ,  Takashi Ito ,  Hirofumi Mukai ,  Masanao Sato ,  Masaaki Terasawa ,  Kenichi Kuroda ,  Kazuyoshi Shiba

发明人： Kiyoshi MATSUBARA ,  Naoki Yashiki ,  Shiro Baba ,  Takashi Ito ,  Hirofumi Mukai ,  Masanao Sato ,  Masaaki Terasawa ,  Kenichi Kuroda ,  Kazuyoshi Shiba

IPC分类号： G06F13/00

CPC分类号： H01L27/11526 ,  G06F9/445 ,  G06F15/7814 ,  G06F15/7821 ,  G11C7/1045 ,  G11C16/0416 ,  G11C16/102 ,  G11C16/105 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3445 ,  G11C16/3459 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11531 ,  H01L27/11546 ,  Y02D10/43

摘要： A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.

摘要翻译： 具有电可擦除和可编程非易失性存储器的半导体器件，例如，包括以行和列布置的存储器单元的可重写非易失性存储器，并且被设置为便于闪存擦除以及多个存储器单元的各个单元的选择性擦除。 用作微计算机芯片的半导体器件还具有处理单元，并且包括：输入端子，用于在处理单元的控制下在闪速存储器被重写的第一操作模式和第二操作模式之间接收用于切换微型计算机的操作模式信号 操作模式，其中在外部连接到微型计算机的分离的写入电路的控制下闪存被重写。