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    Reducing charging effects in charged-particle-beam lithography
    4.
    发明授权
    Reducing charging effects in charged-particle-beam lithography 失效
    减少带电粒子束光刻中的充电效应

    公开(公告)号：US4323638A

    公开(公告)日：1982-04-06

    申请号：US178988

    申请日：1980-08-18

    申请人： Arthur C. Adams ,  Frank B. Alexander, Jr. ,  Hyman J. Levinstein ,  Louis R. Thibault

    发明人： Arthur C. Adams ,  Frank B. Alexander, Jr. ,  Hyman J. Levinstein ,  Louis R. Thibault

    IPC分类号： H01L21/027 ,  B05D3/06

    CPC分类号： H01L21/0271 ,  H01L21/0277 ,  Y10S430/143

    摘要： In a charged-particle-beam lithographic system, charge accumulation on the workpiece during alignment or writing can cause significant pattern placement errors. A film (16) formed directly under the resist layer (56) to be patterned is utilized as a charge-conducting medium during lithography. The pattern delineated in the resist layer (56) is transferred into the film (16) and subsequently into an underlying layer (20). The film (16) is highly compatible with standard lithographic and etching processes used to fabricate LSI and VLSI circuits.

    摘要翻译： 在带电粒子束光刻系统中，对准或写入期间工件上的电荷累积可能导致显着的图案放置误差。 在光刻过程中，作为导电介质，利用形成在图案化抗蚀剂层（56）正下方的膜（16）。 在抗蚀剂层（56）中描绘的图案被转移到膜（16）中并随后转移到下层（20）中。 薄膜（16）与用于制造LSI和VLSI电路的标准光刻和蚀刻工艺高度兼容。

    Deposition of doped silicon oxide films
    5.
    发明授权
    Deposition of doped silicon oxide films 失效
    沉积掺杂氧化硅膜

    公开(公告)号：US4217375A

    公开(公告)日：1980-08-12

    申请号：US829188

    申请日：1977-08-30

    申请人： Arthur C. Adams

    发明人： Arthur C. Adams

    IPC分类号： H01L21/225 ,  H01L21/316 ,  H01L21/18

    CPC分类号： H01L21/02129 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/2255 ,  H01L21/31625

    摘要： A method of depositing doped silicon dioxide layers in the fabrication of semiconductor devices has been found. This method entails the reaction of a mixture of silane, nitrous oxide and a source of a dopant, e.g., phosphine or diborane. The reaction is performed at relatively high temperature, typically between 800 and 900 degrees C., and excellent step coverage is obtained. Further, the pinhole problems previously associated with high temperature techniques are avoided. Lower dopant concentrations, e.g., below 6%, are also practical.

    摘要翻译： 已经发现在制造半导体器件中沉积掺杂二氧化硅层的方法。 该方法需要硅烷，一氧化二氮和掺杂剂源（例如膦或乙硼烷）的混合物的反应。 反应在相对高的温度下进行，通常在800-900℃之间，并获得优异的步骤覆盖。 此外，避免了先前与高温技术相关的针孔问题。 较低的掺杂剂浓度，例如低于6％，也是实用的。

    Method for producing devices comprising high density amorphous silicon or germanium layers by low pressure CVD technique
    6.
    发明授权
    Method for producing devices comprising high density amorphous silicon or germanium layers by low pressure CVD technique 失效
    通过低压CVD技术制造包括高密度非晶硅或锗层的器件的方法

    公开(公告)号：US4357179A

    公开(公告)日：1982-11-02

    申请号：US220121

    申请日：1980-12-23

    申请人： Arthur C. Adams ,  David E. Aspnes ,  Brian G. Bagley

    发明人： Arthur C. Adams ,  David E. Aspnes ,  Brian G. Bagley

    IPC分类号： C23C16/06 ,  C23C16/24 ,  H01L21/205

    CPC分类号： H01L21/02532 ,  C23C16/06 ,  C23C16/24 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262

    摘要： Layers of controllably dopable amorphous silicon and germanium can be produced by means of low pressure chemical vapor deposition, at a reaction temperature between about 450.degree. C. and about 630.degree. C., for Si, and between about 350.degree. C. and about 400.degree. C. for Ge, in an atmosphere comprising a Si-yielding or Ge-yielding precursor such as SiH.sub.4 or GeI.sub.4, at a pressure between about 0.05 Torr and about 0.7 Torr, preferably between about 0.2 and 0.4 Torr. For undoped Si and P-doped Si, the preferred temperature range is from about 550.degree. C. to about 630.degree. C., for B-doped Si, it is from about 480.degree. C. to about 540.degree. C. The material produced has a density in excess of 0.9 of the corresponding crystalline density, and contains less than 1 atomic percent of hydrogen. An advantageous doping method is addition of dopant-forming precursor, e.g., PH.sub.3 or B.sub.2 H.sub.6, to the atmosphere. The material produced can be transformed into high quality crystalline material, and has many device applications in amorphous form, e.g., in solar cells, vidicon tubes, photocopying, and in integrated circuits, either as a conductor or nonconductor. The layers produced show conformal step coverage.

    摘要翻译： 可控制的可掺杂的非晶硅和锗的层可以通过低压化学气相沉积在约450℃至约630℃的反应温度，对于Si和约350℃至约400℃ 在包含Si产生或Ge产生的前体如SiH 4或GeI 4的气氛中，在约0.05托和约0.7托之间的压力下，优选在约0.2和0.4托之间的气氛中。 对于未掺杂的Si和P掺杂的Si，优选的温度范围为约550℃至约630℃，对于B掺杂的Si，其为约480℃至约540℃。产生的材料 具有超过相应结晶密度的0.9的密度，并且含有小于1原子％的氢。 有利的掺杂方法是向大气中添加掺杂剂形成前体，例如PH 3或B 2 H 6。 所生产的材料可以转化成高质量的结晶材料，并且具有非晶形式的许多器件应用，例如在太阳能电池，摄像管，复印以及作为导体或非导体的集成电路中。 所生产的层显示出适形阶梯覆盖。

    Method of producing SOI devices
    7.
    发明授权
    Method of producing SOI devices 失效
    制造SOI器件的方法

    公开(公告)号：US4752590A

    公开(公告)日：1988-06-21

    申请号：US898326

    申请日：1986-08-20

    申请人： Arthur C. Adams ,  Loren N. Pfeiffer ,  Kenneth W. West

    发明人： Arthur C. Adams ,  Loren N. Pfeiffer ,  Kenneth W. West

    IPC分类号： H01L27/00 ,  C30B13/00 ,  H01L21/20 ,  H01L21/324 ,  H01L21/265 ,  C30B13/06

    CPC分类号： C30B29/06 ,  C30B13/00 ,  H01L21/2022 ,  H01L21/324

    摘要： Disclosed are methods that result in substantial improvement of silicon-on-insulator (SOI) device manufacture. We have discovered that carbon can be advantageously used as a wetting agent in the melting-recrystallization (MR) method of producing SOI wafers. We have also found that contacting the wafer (typically subsequent to the formation thereon of a poly-Si layer on a SiO.sub.2 layer but prior to the completion of formation of a SiO.sub.2 cap layer on the poly-Si layer) with an atmosphere that comprises a wetting agent-containing molecular species (e.g., CH.sub.4, NH.sub.3), with the wafer at an appropriate elevated (e.g., 500.degree.-900.degree. C.) temperature, can reliably result in recrystallized Si films of high quality. Furthermore, we have discovered the existence of a previously unknown parameter regime (low thermal gradient across the resolidification front, typically no more than about 4.degree. C./mm) for the MR process that can result in a highly perfect (.chi.min of 3%, subboundary spacing of about 50 .mu.m, misalignment across subboundaries of the order of 0.1.degree.) resolidified Si layer. Devices can be fabricated directly in this layer, or the layer can be used as seed substrate for the growth of a "thick" epitaxial Si layer of the type useful for the fabrication of high voltage semiconductor devices.

    摘要翻译： 公开了导致绝缘体上硅（SOI）器件制造的实质性改进的方法。 我们已经发现，在制造SOI晶片的熔融再结晶（MR）方法中，碳可以有利地用作润湿剂。 我们还发现，与包含一个或多个Si的气氛相接触的晶片（通常在其上形成SiO 2层上的多晶硅层，但是在多晶Si层上形成SiO 2覆盖层之前） 含有润湿剂的分子种类（如CH4，NH3），晶片在适当升高（例如500-900℃）的温度下可以可靠地得到高质量的再结晶Si膜。 此外，我们已经发现，对于MR过程，存在先前未知的参数方案（在再凝固前沿的低热梯度，通常不超过约4℃/ mm），这可以导致高度完美的（3分钟的3分 ％，边界间距约为50微米，跨越子边界的偏差为0.1度）。 器件可以直接在该层中制造，或者该层可以用作种子衬底，用于生长可用于制造高电压半导体器件的类型的“厚”外延Si层。