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    Sub-picosecond resolution segmented re-circulating stochastic time-to-digital converter
    1.
    发明授权
    Sub-picosecond resolution segmented re-circulating stochastic time-to-digital converter 有权
    次皮秒分辨率分段重新循环随机时间 - 数字转换器

    公开(公告)号：US08390349B1

    公开(公告)日：2013-03-05

    申请号：US13533341

    申请日：2012-06-26

    申请人： Ashoke Ravi ,  Ofir Degani ,  Hyung Seok Kim ,  Hasnain Lakdawala ,  Yee W. Li ,  Paolo Madoglio

    发明人： Ashoke Ravi ,  Ofir Degani ,  Hyung Seok Kim ,  Hasnain Lakdawala ,  Yee W. Li ,  Paolo Madoglio

    IPC分类号： H03L7/06

    CPC分类号： G04F10/005 ,  H03L2207/50

    摘要： Disclosed is a method and apparatus to extend TDC resolution to better than 1 ps without incurring a matching and power penalty. Higher resolution can be achieved by segmenting the resolution between a mismatch free re-circulating time-to-digital converter (RTDC) and a stochastic time-to-digital converter (STDC). The disclosed RTDC replicates the same delay element to eliminate mismatch with the required dynamic range (200 ps for a 5 GHz example) and moderate resolution (3-5 ps typical corresponding to 6-7 bits for the 5 GHz case). While the STDC can achieve a resolution of 50 fs but with a range of only 3-5 ps which also corresponds to approximately 6-7 additional bits by exploiting process variations and mismatch to achieve a very fine resolution with limited dynamic range.

    摘要翻译： 公开了一种将TDC分辨率提高到1ps而不引起匹配和功率损失的方法和装置。 可以通过在不匹配的循环时间数字转换器（RTDC）和随机时间 - 数字转换器（STDC）之间分辨分辨率来实现更高的分辨率。 所公开的RTDC复制相同的延迟元件以消除与所需动态范围（对于5GHz示例为200ps）和中等分辨率（3-5ps典型对应于5GHz情况下的6-7位）的失配。 虽然STDC可以实现50 fs的分辨率，但只有3-5 ps的范围，这也通过利用过程变化和失配来对应于大约6-7个附加位，以获得有限动态范围的非常精细的分辨率。

    RESISTOR-BASED SIGMA-DELTA DAC
    3.
    发明申请
    RESISTOR-BASED SIGMA-DELTA DAC 有权
    基于电阻的SIGMA-DELTA DAC

    公开(公告)号：US20130271305A1

    公开(公告)日：2013-10-17

    申请号：US13995156

    申请日：2011-09-30

    申请人： Hyung Seok Kim ,  Yee W. Li ,  Ashoke Ravi ,  Hasnain Lakdawala

    发明人： Hyung Seok Kim ,  Yee W. Li ,  Ashoke Ravi ,  Hasnain Lakdawala

    IPC分类号： H03M3/00 ,  H03M1/78

    CPC分类号： H03M3/50 ,  G09G3/3688 ,  H03M1/00 ,  H03M1/0863 ,  H03M1/12 ,  H03M1/747 ,  H03M1/785 ,  H03M1/808 ,  H03M3/30 ,  H03M3/502

    摘要： An inverter-driven resistor-ladder digital-to-analog (DAC) converter includes a resistor-ladder network that comprises a resistor for each bit signal of a multi-bit input signal. Each resistor of the resistor-ladder network comprises an input end and an output end. The input end of each resistor is coupled to a corresponding bit signal of the multi-bit input signal, and the output end of each resistor is coupled to an output node of the resistor-ladder network. An output voltage is generated at the output node that is based on the multi-bit input signal. In one exemplary embodiment, the multi-bit input signal is a sigma-delta (ΣΔ) modulated multi-bit input signal. In another exemplary embodiment, resistance values of the resistors of the resistor-ladder network are related by a binary weighting. In still another exemplary embodiment, resistance values of the resistors of the resistor-ladder network are substantially equal.

    摘要翻译： 逆变器驱动的电阻梯形数模（DAC）转换器包括一个电阻梯形网络，包括一个多位输入信号的每个位信号的电阻。 电阻梯形网络的每个电阻器包括输入端和输出端。 每个电阻器的输入端耦合到多位输入信号的对应位信号，并且每个电阻器的输出端耦合到电阻梯形网络的输出节点。 在输出节点处产生基于多位输入信号的输出电压。 在一个示例性实施例中，多位输入信号是Σ-Δ（SigmaDelta）调制的多位输入信号。 在另一示例性实施例中，电阻梯形网络的电阻器的电阻值通过二进制加权相关。 在又一示例性实施例中，电阻梯形网络的电阻器的电阻值基本相等。

    Resistor-based Σ-ΔDAC
    4.
    发明授权
    Resistor-based Σ-ΔDAC 有权
    基于电阻和电阻的DAC

    公开(公告)号：US08941520B2

    公开(公告)日：2015-01-27

    申请号：US13995156

    申请日：2011-09-30

    申请人： Hyung Seok Kim ,  Yee W. Li ,  Ashoke Ravi ,  Hasnain Lakdawala

    发明人： Hyung Seok Kim ,  Yee W. Li ,  Ashoke Ravi ,  Hasnain Lakdawala

    IPC分类号： H03M3/00 ,  H03M1/08 ,  H03M1/80 ,  H03M1/78 ,  H03M1/74 ,  H03M1/00 ,  H03M1/12 ,  G09G3/36

    CPC分类号： H03M3/50 ,  G09G3/3688 ,  H03M1/00 ,  H03M1/0863 ,  H03M1/12 ,  H03M1/747 ,  H03M1/785 ,  H03M1/808 ,  H03M3/30 ,  H03M3/502

    摘要： An inverter-driven resistor-ladder digital-to-analog (DAC) converter includes a resistor-ladder network that comprises a resistor for each bit signal of a multi-bit input signal. Each resistor of the resistor-ladder network comprises an input end and an output end. The input end of each resistor is coupled to a corresponding bit signal of the multi-bit input signal, and the output end of each resistor is coupled to an output node of the resistor-ladder network. An output voltage is generated at the output node that is based on the multi-bit input signal. In one exemplary embodiment, the multi-bit input signal is a sigma-delta (ΣΔ) modulated multi-bit input signal. In another exemplary embodiment, resistance values of the resistors of the resistor-ladder network are related by a binary weighting. In still another exemplary embodiment, resistance values of the resistors of the resistor-ladder network are substantially equal.

    摘要翻译： 逆变器驱动的电阻梯形数模（DAC）转换器包括一个电阻梯形网络，包括一个多位输入信号的每个位信号的电阻。 电阻梯形网络的每个电阻器包括输入端和输出端。 每个电阻器的输入端耦合到多位输入信号的对应位信号，并且每个电阻器的输出端耦合到电阻梯形网络的输出节点。 在输出节点处产生基于多位输入信号的输出电压。 在一个示例性实施例中，多比特输入信号是Σ-Δ（＆Sgr＆amp; Dgr）调制的多位输入信号。 在另一示例性实施例中，电阻梯形网络的电阻器的电阻值通过二进制加权相关。 在又一示例性实施例中，电阻梯形网络的电阻器的电阻值基本相等。

    Stochastic beating time-to-digital converter (TDC)
    5.
    发明授权
    Stochastic beating time-to-digital converter (TDC) 失效
    随机抖动时间 - 数字转换器（TDC）

    公开(公告)号：US08773182B1

    公开(公告)日：2014-07-08

    申请号：US13756670

    申请日：2013-02-01

    申请人： Ofir Degani ,  Ashoke Ravi ,  Hasnain Lakdawala ,  Rotem Banin

    发明人： Ofir Degani ,  Ashoke Ravi ,  Hasnain Lakdawala ,  Rotem Banin

    IPC分类号： H03L7/06

    CPC分类号： H03L7/085 ,  G04F10/005 ,  H03L2207/50

    摘要： A stochastic beating time-to-digital converter (TDC) can include triggered ring oscillator (TRO) and a stochastic TDC (sTDC). The TRO, when triggered by a reference signal edge, can generate a periodic TRO signal with a TRO period that is a selected ratio of a voltage-controlled oscillator (VCO) period. The TRO period can be greater than or less than the VCO period by the specified ratio. The sTDC with an event triggered memory can include an sTDC component with a plurality of groups of latches. Each group of latches can be configured to sample and store a VCO state at an edge of a TRO signal. The sTDC component can trigger a capture of a select number of VCO states of the group of latches when one latch in the group of latches transitions to a different digital state referred to as a transition edge.

    摘要翻译： 随机抖动时间 - 数字转换器（TDC）可以包括触发环形振荡器（TRO）和随机TDC（sTDC）。 当由参考信号沿触发时，TRO可以产生具有作为压控振荡器（VCO）周期的选定比率的TRO周期的周期性TRO信号。 TRO周期可以大于或小于VCO周期的指定比率。 具有事件触发的存储器的sTDC可以包括具有多组锁存器的sTDC组件。 每组锁存器可以配置为在TRO信号的边沿采样和存储VCO状态。 当锁存器组中的一个锁存器转变为被称为过渡沿的不同数字状态时，sTDC组件可以触发锁存器组的选定数量的VCO状态的捕获。

    Film bulk acoustic resonator calibration
    6.
    发明授权
    Film bulk acoustic resonator calibration 失效
    薄膜体声共振器校准

    公开(公告)号：US07576621B2

    公开(公告)日：2009-08-18

    申请号：US11823856

    申请日：2007-06-28

    申请人： Hasnain Lakdawala ,  Ofir Degani ,  Ashoke Ravi ,  Masoud Sajadieh ,  Soumyanath Krishnamurthy

    发明人： Hasnain Lakdawala ,  Ofir Degani ,  Ashoke Ravi ,  Masoud Sajadieh ,  Soumyanath Krishnamurthy

    IPC分类号： H03L1/00

    CPC分类号： H03L1/026 ,  H03L7/1974

    摘要： Film bulk acoustic resonators (FBARS) have resonant frequencies that vary with manufacturing variations, but tend to be matched when in proximity on an integrated circuit die. FBAR resonant frequency is determined using a fractional-N synthesizer and comparing phase/frequency of an output signal from the fractional-N synthesizer to a reference. The reference may be derived from a low frequency crystal oscillator, an external signal source, or a communications signal.

    摘要翻译： 薄膜体声共振器（FBARS）具有随着制造变化而变化的谐振频率，但是当在集成电路芯片附近时，它们倾向于匹配。 使用分数N合成器确定FBAR谐振频率，并将来自分数N合成器的输出信号的相位/频率与参考值进行比较。 该参考可以从低频晶体振荡器，外部信号源或通信信号导出。

    FEEDBACK CALIBRATION OF DIGITAL TO TIME CONVERTER
    7.
    发明申请
    FEEDBACK CALIBRATION OF DIGITAL TO TIME CONVERTER 有权
    数字到时间转换器的反馈校准

    公开(公告)号：US20150188583A1

    公开(公告)日：2015-07-02

    申请号：US14140801

    申请日：2013-12-26

    申请人： Ashoke Ravi ,  Ofir Degani ,  Hasnain Lakdawala

    发明人： Ashoke Ravi ,  Ofir Degani ,  Hasnain Lakdawala

    IPC分类号： H04B1/04 ,  H03M1/84

    CPC分类号： H04B17/21 ,  H03F1/3241 ,  H03M1/1009 ,  H03M1/82 ,  H03M1/84 ,  H04B1/0475 ,  H04B2001/0425

    摘要： This document discusses apparatus and methods for compensating non-linearity of digital-to-time converters (DTCs). In an example, a wireless device can include a digital-to-time converter (DTC) configured to receive a phase data information from a baseband processor and to provide a first modulation signal for generating a wireless signal, a detector configure to receive the first modulation signal and provide an indication of nonlinearities of the DTC, and a pre-distortion module configured to provide pre-distortion information to the DTC using the indication of nonlinearities.

    摘要翻译： 本文讨论了用于补偿数字到时间转换器（DTC）的非线性的装置和方法。 在一个示例中，无线设备可以包括被配置为从基带处理器接收相位数据信息并提供用于生成无线信号的第一调制信号的数字 - 时间转换器（DTC），检测器配置为接收第一 调制信号并提供DTC的非线性指示，以及被配置为使用非线性指示向DTC提供预失真信息的预失真模块。

    Digital Voltage Ramp Generator
    8.
    发明申请
    Digital Voltage Ramp Generator 审中-公开
    数字电压斜坡发生器

    公开(公告)号：US20150116012A1

    公开(公告)日：2015-04-30

    申请号：US14066961

    申请日：2013-10-30

    申请人： Hasnain Lakdawala ,  Eshel Gordon ,  Ofir Degani ,  Ashoke Ravi ,  Thomas W. Brown

    发明人： Hasnain Lakdawala ,  Eshel Gordon ,  Ofir Degani ,  Ashoke Ravi ,  Thomas W. Brown

    IPC分类号： H03K4/12

    CPC分类号： H03K4/12 ,  H03K4/48 ,  H03K4/502

    摘要： According to some embodiments, an all digital ramp generator may use a string of series connected delays or digital to time-based circuits to perform voltage ramp generation. Thus in some embodiments conventional operational amplifier circuits and relaxation oscillators may be replaced for generating triangular ramp waveforms for DC to DC or direct time-based DC to DC converters. The use of delay lines may produce sufficient resolution for many applications. Thus time domain techniques may afford a more digital approach that scales with process technology and allows high speed operation in some embodiments. A design based on use of inverters and capacitors may scale well with process technology. The decoder and drive logic may be integrated into the voltage ramp generation in some embodiments.

    摘要翻译： 根据一些实施例，全数字斜坡发生器可以使用串联连接的延迟串或数字到基于时间的电路来执行电压斜坡生成。 因此，在一些实施例中，常规运算放大器电路和弛豫振荡器可以被替换以产生用于直流到直流或直接基于时间的直流到直流转换器的三角形斜坡波形。 使用延迟线可以为许多应用产生足够的分辨率。 因此，时域技术可以提供与数字处理技术相比较的数字化方法，并且在一些实施例中允许高速操作。 基于逆变器和电容器的设计可以与工艺技术相结合。 在一些实施例中，解码器和驱动逻辑可以集成到电压斜坡生成中。