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    Sub-picosecond resolution segmented re-circulating stochastic time-to-digital converter
    1.
    发明授权
    Sub-picosecond resolution segmented re-circulating stochastic time-to-digital converter 有权
    次皮秒分辨率分段重新循环随机时间 - 数字转换器

    公开(公告)号：US08390349B1

    公开(公告)日：2013-03-05

    申请号：US13533341

    申请日：2012-06-26

    申请人： Ashoke Ravi ,  Ofir Degani ,  Hyung Seok Kim ,  Hasnain Lakdawala ,  Yee W. Li ,  Paolo Madoglio

    发明人： Ashoke Ravi ,  Ofir Degani ,  Hyung Seok Kim ,  Hasnain Lakdawala ,  Yee W. Li ,  Paolo Madoglio

    IPC分类号： H03L7/06

    CPC分类号： G04F10/005 ,  H03L2207/50

    摘要： Disclosed is a method and apparatus to extend TDC resolution to better than 1 ps without incurring a matching and power penalty. Higher resolution can be achieved by segmenting the resolution between a mismatch free re-circulating time-to-digital converter (RTDC) and a stochastic time-to-digital converter (STDC). The disclosed RTDC replicates the same delay element to eliminate mismatch with the required dynamic range (200 ps for a 5 GHz example) and moderate resolution (3-5 ps typical corresponding to 6-7 bits for the 5 GHz case). While the STDC can achieve a resolution of 50 fs but with a range of only 3-5 ps which also corresponds to approximately 6-7 additional bits by exploiting process variations and mismatch to achieve a very fine resolution with limited dynamic range.

    摘要翻译： 公开了一种将TDC分辨率提高到1ps而不引起匹配和功率损失的方法和装置。 可以通过在不匹配的循环时间数字转换器（RTDC）和随机时间 - 数字转换器（STDC）之间分辨分辨率来实现更高的分辨率。 所公开的RTDC复制相同的延迟元件以消除与所需动态范围（对于5GHz示例为200ps）和中等分辨率（3-5ps典型对应于5GHz情况下的6-7位）的失配。 虽然STDC可以实现50 fs的分辨率，但只有3-5 ps的范围，这也通过利用过程变化和失配来对应于大约6-7个附加位，以获得有限动态范围的非常精细的分辨率。

    RESISTOR-BASED SIGMA-DELTA DAC
    2.
    发明申请
    RESISTOR-BASED SIGMA-DELTA DAC 有权
    基于电阻的SIGMA-DELTA DAC

    公开(公告)号：US20130271305A1

    公开(公告)日：2013-10-17

    申请号：US13995156

    申请日：2011-09-30

    申请人： Hyung Seok Kim ,  Yee W. Li ,  Ashoke Ravi ,  Hasnain Lakdawala

    发明人： Hyung Seok Kim ,  Yee W. Li ,  Ashoke Ravi ,  Hasnain Lakdawala

    IPC分类号： H03M3/00 ,  H03M1/78

    CPC分类号： H03M3/50 ,  G09G3/3688 ,  H03M1/00 ,  H03M1/0863 ,  H03M1/12 ,  H03M1/747 ,  H03M1/785 ,  H03M1/808 ,  H03M3/30 ,  H03M3/502

    摘要： An inverter-driven resistor-ladder digital-to-analog (DAC) converter includes a resistor-ladder network that comprises a resistor for each bit signal of a multi-bit input signal. Each resistor of the resistor-ladder network comprises an input end and an output end. The input end of each resistor is coupled to a corresponding bit signal of the multi-bit input signal, and the output end of each resistor is coupled to an output node of the resistor-ladder network. An output voltage is generated at the output node that is based on the multi-bit input signal. In one exemplary embodiment, the multi-bit input signal is a sigma-delta (ΣΔ) modulated multi-bit input signal. In another exemplary embodiment, resistance values of the resistors of the resistor-ladder network are related by a binary weighting. In still another exemplary embodiment, resistance values of the resistors of the resistor-ladder network are substantially equal.

    摘要翻译： 逆变器驱动的电阻梯形数模（DAC）转换器包括一个电阻梯形网络，包括一个多位输入信号的每个位信号的电阻。 电阻梯形网络的每个电阻器包括输入端和输出端。 每个电阻器的输入端耦合到多位输入信号的对应位信号，并且每个电阻器的输出端耦合到电阻梯形网络的输出节点。 在输出节点处产生基于多位输入信号的输出电压。 在一个示例性实施例中，多位输入信号是Σ-Δ（SigmaDelta）调制的多位输入信号。 在另一示例性实施例中，电阻梯形网络的电阻器的电阻值通过二进制加权相关。 在又一示例性实施例中，电阻梯形网络的电阻器的电阻值基本相等。

    Resistor-based Σ-ΔDAC
    3.
    发明授权
    Resistor-based Σ-ΔDAC 有权
    基于电阻和电阻的DAC

    公开(公告)号：US08941520B2

    公开(公告)日：2015-01-27

    申请号：US13995156

    申请日：2011-09-30

    申请人： Hyung Seok Kim ,  Yee W. Li ,  Ashoke Ravi ,  Hasnain Lakdawala

    发明人： Hyung Seok Kim ,  Yee W. Li ,  Ashoke Ravi ,  Hasnain Lakdawala

    IPC分类号： H03M3/00 ,  H03M1/08 ,  H03M1/80 ,  H03M1/78 ,  H03M1/74 ,  H03M1/00 ,  H03M1/12 ,  G09G3/36

    CPC分类号： H03M3/50 ,  G09G3/3688 ,  H03M1/00 ,  H03M1/0863 ,  H03M1/12 ,  H03M1/747 ,  H03M1/785 ,  H03M1/808 ,  H03M3/30 ,  H03M3/502

    摘要： An inverter-driven resistor-ladder digital-to-analog (DAC) converter includes a resistor-ladder network that comprises a resistor for each bit signal of a multi-bit input signal. Each resistor of the resistor-ladder network comprises an input end and an output end. The input end of each resistor is coupled to a corresponding bit signal of the multi-bit input signal, and the output end of each resistor is coupled to an output node of the resistor-ladder network. An output voltage is generated at the output node that is based on the multi-bit input signal. In one exemplary embodiment, the multi-bit input signal is a sigma-delta (ΣΔ) modulated multi-bit input signal. In another exemplary embodiment, resistance values of the resistors of the resistor-ladder network are related by a binary weighting. In still another exemplary embodiment, resistance values of the resistors of the resistor-ladder network are substantially equal.

    摘要翻译： 逆变器驱动的电阻梯形数模（DAC）转换器包括一个电阻梯形网络，包括一个多位输入信号的每个位信号的电阻。 电阻梯形网络的每个电阻器包括输入端和输出端。 每个电阻器的输入端耦合到多位输入信号的对应位信号，并且每个电阻器的输出端耦合到电阻梯形网络的输出节点。 在输出节点处产生基于多位输入信号的输出电压。 在一个示例性实施例中，多比特输入信号是Σ-Δ（＆Sgr＆amp; Dgr）调制的多位输入信号。 在另一示例性实施例中，电阻梯形网络的电阻器的电阻值通过二进制加权相关。 在又一示例性实施例中，电阻梯形网络的电阻器的电阻值基本相等。

    RE-CIRCULATING TIME-TO-DIGITAL CONVERTER (TDC)
    4.
    发明申请
    RE-CIRCULATING TIME-TO-DIGITAL CONVERTER (TDC) 有权
    再循环数字时间转换器（TDC）

    公开(公告)号：US20140333358A1

    公开(公告)日：2014-11-13

    申请号：US13997229

    申请日：2012-04-10

    申请人： Hyung Seok Kim ,  Ashoke Ravi ,  William Y. Li ,  Kailash Chandrashekar

    发明人： Hyung Seok Kim ,  Ashoke Ravi ,  William Y. Li ,  Kailash Chandrashekar

    IPC分类号： H04L7/033 ,  G04F10/00

    CPC分类号： H04L7/0331 ,  G04F10/005 ,  H03L7/1974

    摘要： A re-circulating time-to-digital converter (TDC) can include a triggered reference ring oscillator (TRRO) and a delay module. The triggered reference ring oscillator can, when triggered by a reference signal edge, generate a periodic ring oscillator signal with a ring oscillator period that is a selected ratio of a voltage-controlled oscillator (VCO) period. The delay module can store, in a plurality of latches, samples of a VCO signal docked by the periodic ring oscillator signal. Each latch can generate an output of the sample, and each latch output can represent a time difference polarity between VCO signal and TRRO signal. In another example, the re-circulating TDC can include the triggered reference ring oscillator, a digital frequency lock module, and a TDC post-process module. The digital frequency lock module can generate a ring oscillator control signal, which sets the ring oscillator period for the triggered reference ring oscillator. The TDC post-process module can generate a TDC output, which can be a binary representation of a phase difference between a reference signal and a VCO signal.

    摘要翻译： 再循环时间 - 数字转换器（TDC）可以包括触发参考环形振荡器（TRRO）和延迟模块。 触发的参考环形振荡器可以在由参考信号边沿触发时产生周期性环形振荡器信号，其环路振荡器周期是压控振荡器（VCO）周期的选定比率。 延迟模块可以在多个锁存器中存储由周期性环形振荡器信号对接的VCO信号的采样。 每个锁存器可以产生采样的输出，并且每个锁存器输出可以表示VCO信号和TRRO信号之间的时差极性。 在另一示例中，再循环TDC可以包括触发的参考环形振荡器，数字频率锁定模块和TDC后处理模块。 数字频率锁定模块可以产生环形振荡器控制信号，为触发的参考环形振荡器设置环形振荡器周期。 TDC后处理模块可以产生TDC输出，其可以是参考信号和VCO信号之间的相位差的二进制表示。

    Re-circulating time-to-digital converter (TDC)
    5.
    发明授权
    Re-circulating time-to-digital converter (TDC) 有权
    再循环时间数字转换器（TDC）

    公开(公告)号：US09197402B2

    公开(公告)日：2015-11-24

    申请号：US13997229

    申请日：2012-04-10

    申请人： Hyung Seok Kim ,  Ashoke Ravi ,  William Y. Li ,  Kailash Chandrashekar

    发明人： Hyung Seok Kim ,  Ashoke Ravi ,  William Y. Li ,  Kailash Chandrashekar

    IPC分类号： H03M1/48 ,  H04L7/033 ,  H03L7/197 ,  G04F10/00

    CPC分类号： H04L7/0331 ,  G04F10/005 ,  H03L7/1974

    摘要： A re-circulating time-to-digital converter (TDC) can include a triggered reference ring oscillator (TRRO) and a delay module. The triggered reference ring oscillator can, when triggered by a reference signal edge, generate a periodic ring oscillator signal with a ring oscillator period that is a selected ratio of a voltage-controlled oscillator (VCO) period. The delay module can store, in a plurality of latches, samples of a VCO signal docked by the periodic ring oscillator signal. Each latch can generate an output of the sample, and each latch output can represent a time difference polarity between VCO signal and TRRO signal. In another example, the re-circulating TDC can include the triggered reference ring oscillator, a digital frequency lock module, and a TDC post-process module. The digital frequency lock module can generate a ring oscillator control signal, which sets the ring oscillator period for the triggered reference ring oscillator. The TDC post-process module can generate a TDC output, which can be a binary representation of a phase difference between a reference signal and a VCO signal.

    摘要翻译： 再循环时间 - 数字转换器（TDC）可以包括触发参考环形振荡器（TRRO）和延迟模块。 触发的参考环形振荡器可以在由参考信号边沿触发时产生周期性环形振荡器信号，其环路振荡器周期是压控振荡器（VCO）周期的选定比率。 延迟模块可以在多个锁存器中存储由周期性环形振荡器信号对接的VCO信号的采样。 每个锁存器可以产生采样的输出，并且每个锁存器输出可以表示VCO信号和TRRO信号之间的时差极性。 在另一示例中，再循环TDC可以包括触发的参考环形振荡器，数字频率锁定模块和TDC后处理模块。 数字频率锁定模块可以产生环形振荡器控制信号，为触发的参考环形振荡器设置环形振荡器周期。 TDC后处理模块可以产生TDC输出，其可以是参考信号和VCO信号之间的相位差的二进制表示。

    Semiconductor memory device and method of operating the same
    6.
    发明授权
    Semiconductor memory device and method of operating the same 有权
    半导体存储器件及其操作方法

    公开(公告)号：US08526239B2

    公开(公告)日：2013-09-03

    申请号：US13096870

    申请日：2011-04-28

    申请人： Hyung Seok Kim

    发明人： Hyung Seok Kim

    IPC分类号： G11C16/06 ,  G11C16/04

    CPC分类号： G11C16/26 ,  G11C16/344

    摘要： A semiconductor memory device includes a memory string coupled to a bit line, a page buffer configured to sense a sensing current of the bit line in an erase verification operation or a program verification operation, and a sensing control circuit configured to differently set a level of the sensing current in the erase verification operation and the program verification operation in order to sense the threshold voltage level of a selected memory cell of the memory string.

    摘要翻译： 半导体存储器件包括耦合到位线的存储器串，配置为在擦除验证操作或程序验证操作中感测位线的感测电流的页缓冲器，以及感测控制电路，其被配置为不同地设置 擦除验证操作中的感测电流和程序验证操作，以便感测存储器串的选定存储单元的阈值电压电平。