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    Method of producing epitaxial layers of II-VI semiconductors with high acceptor concentrations
    3.
    发明授权
    Method of producing epitaxial layers of II-VI semiconductors with high acceptor concentrations 失效
    制备具有高受主浓度的II-VI半导体外延层的方法

    公开(公告)号：US5227328A

    公开(公告)日：1993-07-13

    申请号：US851452

    申请日：1992-03-16

    申请人： Babar A. Khan ,  Nikhil R. Taskar

    发明人： Babar A. Khan ,  Nikhil R. Taskar

    IPC分类号： H01L21/38

    CPC分类号： H01L21/38 ,  Y10S148/064 ,  Y10S438/902

    摘要： Epitaxial layers of II-VI semiconductors in-situ doped with high concentrations of a stable acceptor-type impurity and capped with a diffusion-limiting layer, when subjected to a rapid thermal anneal at a temperature between 700 and 950 degrees C., exhibit a high conversion of the impurities to acceptors, sufficient to render the layers p-type.

    摘要翻译： 原位掺杂高浓度稳定受主型杂质并用扩散限制层封端的II-VI半导体的外延层当在700和950摄氏度之间的温度下进行快速热退火时，表现出 杂质转化为受体的高转化率，足以使层p型。

    Metal-insulator-metal (MIM) capacitor with deep trench (DT) structure and method in a silicon-on-insulator (SOI)
    8.
    发明授权
    Metal-insulator-metal (MIM) capacitor with deep trench (DT) structure and method in a silicon-on-insulator (SOI) 有权
    具有深沟槽（DT）结构的金属绝缘体金属（MIM）电容器和绝缘体上硅（SOI）

    公开(公告)号：US08946045B2

    公开(公告)日：2015-02-03

    申请号：US13457601

    申请日：2012-04-27

    申请人： John E. Barth, Jr. ,  Herbert L. Ho ,  Babar A. Khan ,  Kirk D. Peterson

    发明人： John E. Barth, Jr. ,  Herbert L. Ho ,  Babar A. Khan ,  Kirk D. Peterson

    IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L29/02

    CPC分类号： H01L28/40 ,  H01L21/84 ,  H01L27/1203 ,  H01L28/91 ,  H01L29/66181 ,  H01L29/945

    摘要： A structure forming a metal-insulator-metal (MIM) trench capacitor is disclosed. The structure comprises a multi-layer substrate having a metal layer and at least one dielectric layer. A trench is etched into the substrate, passing through the metal layer. The trench is lined with a metal material that is in contact with the metal layer, which comprises a first node of a capacitor. A dielectric material lines the metal material in the trench. The trench is filled with a conductor. The dielectric material that lines the metal material separates the conductor from the metal layer and the metal material lining the trench. The conductor comprises a second node of the capacitor.

    摘要翻译： 公开了形成金属 - 绝缘体 - 金属（MIM）沟槽电容器的结构。 该结构包括具有金属层和至少一个电介质层的多层基底。 沟槽被蚀刻到衬底中，穿过金属层。 沟槽衬有与金属层接触的金属材料，金属层包括电容器的第一节点。 电介质材料将沟槽中的金属材料排列。 沟槽填充有导体。 将金属材料排列的电介质材料将导体与金属层和衬套在沟槽上的金属材料分开。 导体包括电容器的第二节点。

    DRAM WITH DUAL LEVEL WORD LINES
    9.
    发明申请
    DRAM WITH DUAL LEVEL WORD LINES 有权

    公开(公告)号：US20140021523A1

    公开(公告)日：2014-01-23

    申请号：US13551766

    申请日：2012-07-18

    申请人： Babar A. Khan ,  Effendi Leobandung

    发明人： Babar A. Khan ,  Effendi Leobandung

    IPC分类号： H01L27/108 ,  H01L21/8242

    CPC分类号： H01L27/10867 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/10891 ,  H01L27/1203 ,  H01L29/945

    摘要： A top semiconductor layer and conductive cap structures over deep trench capacitors are simultaneously patterned by an etch. Each patterned portion of the conductive cap structures constitutes a conductive cap structure, which laterally contacts a semiconductor material portion that is one of patterned remaining portions of the top semiconductor layer. Gate electrodes are formed as discrete structures that are not interconnected. After formation and planarization of a contact-level dielectric layer, passing gate lines are formed above the contact-level dielectric layer in a line level to provide electrical connections to the gate electrodes. Gate electrodes and passing gate lines that are electrically connected among one another constitute a gate line that is present across two levels.