公开(公告)号：US07741857B2

公开(公告)日：2010-06-22

申请号：US12043169

申请日：2008-03-06

申请人： Basanth Jagannathan ,  Zhenrong Jin ,  Hongmei Li

发明人： Basanth Jagannathan ,  Zhenrong Jin ,  Hongmei Li

IPC分类号： G01R35/00 ,  G01D18/00 ,  G01P21/00

CPC分类号： G01R27/32 ,  G01R35/00

摘要： S-parameter data is measured on an embedded device test structure, an open dummy, and a short dummy. A 4-port network of the pad set parasitics of the embedded device test structure is modeled by a parameterized netlist containing a lumped element network having at least one parameterized lumped element. The S-parameter data across a range of measurement frequencies is fitted with the parameterized netlist employing the at least one parameterized lumped element as at least one fitting parameter for the S-parameter data. Thus, the fitting method is a multi-frequency fitting for the at least one parameterized lumped element. A 4-port Y-parameter (admittance parameter) is obtained from the fitted parameterized netlist. The Y-parameter of the device under test is obtained from the measured admittance of the embedded device test structure and the calculated 4-port Y parameter.

摘要翻译： S参数数据是在嵌入式设备测试结构上测量的，一个开放虚拟的和一个短虚拟的。 嵌入式设备测试结构的焊盘组寄生效应的4端口网络由包含具有至少一个参数化集总元件的集总元件网络的参数化网表建模。 跨越测量频率范围的S参数数据与采用至少一个参数化集总元件的参数化网表相配合，作为S参数数据的至少一个拟合参数。 因此，拟合方法是用于至少一个参数化的集总元件的多频率拟合。 从拟合的参数化网表获得4端口Y参数（导纳参数）。 被测器件的Y参数是从嵌入式器件测试结构的测量导纳和计算的4端口Y参数获得的。

公开(公告)号：US20090224772A1

公开(公告)日：2009-09-10

申请号：US12043169

申请日：2008-03-06

申请人： Basanth Jagannathan ,  Zhenrong Jin ,  Hongmei Li

发明人： Basanth Jagannathan ,  Zhenrong Jin ,  Hongmei Li

IPC分类号： G01R35/00

CPC分类号： G01R27/32 ,  G01R35/00

摘要： S-parameter data is measured on an embedded device test structure, an open dummy, and a short dummy. A 4-port network of the pad set parasitics of the embedded device test structure is modeled by a parameterized netlist containing a lumped element network having at least one parameterized lumped element. The S-parameter data across a range of measurement frequencies is fitted with the parametrized netlist employing the at least one parameterized lumped element as at least one fitting parameter for the S-parameter data. Thus, the fitting method is a multi-frequency fitting for the at least one parameterized lumped element. A 4-port Y-parameter (admittance parameter) is obtained from the fitted parameterized netlist. The Y-parameter of the device under test is obtained from the measured admittance of the embedded device test structure and the calculated 4-port Y parameter.

摘要翻译： S参数数据是在嵌入式设备测试结构上测量的，一个开放虚拟的和一个短虚拟的。 嵌入式设备测试结构的焊盘组寄生效应的4端口网络由包含具有至少一个参数化集总元件的集总元件网络的参数化网表建模。 将测量频率范围内的S参数数据与采用至少一个参数化集总元件的参数化网表拟合为S参数数据的至少一个拟合参数。 因此，拟合方法是用于至少一个参数化的集总元件的多频率拟合。 从拟合的参数化网表获得4端口Y参数（导纳参数）。 被测器件的Y参数是从嵌入式器件测试结构的测量导纳和计算的4端口Y参数获得的。

公开(公告)号：US20060071304A1

公开(公告)日：2006-04-06

申请号：US10711640

申请日：2004-09-29

申请人： Basanth Jagannathan ,  John Pekarik ,  Christopher Schnabel

发明人： Basanth Jagannathan ,  John Pekarik ,  Christopher Schnabel

IPC分类号： H01L23/552

CPC分类号： H01L29/78 ,  H01L23/4824 ,  H01L29/1087

摘要： A structure, apparatus and method for a FET prime cell surrounded by a conductor is provided. The surrounding conductor includes a substrate contact arranged proximate a source of the FET. The surrounding conductor may be a ring substrate contact arranged within the substrate of the FET in electrical communication with elongated sources of the FET. No external contacts are needed to the ring substrate contact because no current flows therethrough while the ring substrate contact may act as a collection source for noise such as stray currents.

摘要翻译： 提供了由导体包围的FET素电池的结构，装置和方法。 周围导体包括靠近FET的源极布置的衬底接触。 周围导体可以是布置在FET的衬底内的环形衬底接触，与FET的细长源电连通。 由于没有电流流过其中，环形基板接触可能作为用于诸如杂散电流的噪声的收集源，因此环形基板接触不需要外部接触。

公开(公告)号：US20050145172A1

公开(公告)日：2005-07-07

申请号：US11057176

申请日：2005-02-15

申请人： Jack Chu ,  Basanth Jagannathan ,  Ryan Wuthrich

发明人： Jack Chu ,  Basanth Jagannathan ,  Ryan Wuthrich

IPC分类号： C23C16/44 ,  C23C16/54 ,  C30B25/08 ,  C30B25/14 ,  C23C16/00 ,  C23C16/24

CPC分类号： C23C16/54 ,  C23C16/4412 ,  C30B25/08 ,  C30B25/14 ,  Y10T117/10

摘要： An apparatus and method for forming at least a portion of an electronic device include a High Vacuum-Chemical Vapor Deposition (UHV-CVD) system and a Low Pressure-Chemical Vapor Deposition (LPCVD) system using a common reactor. The invention overcomes the problem, of silicon containing wafers being dipped in HF acid prior to CVD processing, and the problem of surface passivation between processes in multiple CVD reactors.

摘要翻译： 用于形成电子器件的至少一部分的装置和方法包括使用公共反应器的高真空 - 化学气相沉积（UHV-CVD）系统和低压 - 化学气相沉积（LPCVD）系统。 本发明克服了在CVD处理之前将含硅晶片浸入HF酸中的问题，以及在多个CVD反应器中的工艺之间的表面钝化的问题。

公开(公告)号：US20120146104A1

公开(公告)日：2012-06-14

申请号：US13398408

申请日：2012-02-16

申请人： Basanth Jagannathan ,  John J. Pekarik ,  Christopher M. Schnabel

发明人： Basanth Jagannathan ,  John J. Pekarik ,  Christopher M. Schnabel

IPC分类号： H01L29/06

CPC分类号： H01L29/78 ,  H01L23/4824 ,  H01L29/1087

摘要： Method of making a semiconductor device that includes forming a source and a drain in a substrate, forming a gate on the substrate between the source and drain, forming a substrate contact in electrical contact with the source, and forming an electrical contact to the source, drain and gate, and the substrate.

摘要翻译： 制造半导体器件的方法包括在衬底中形成源极和漏极，在源极和漏极之间的衬底上形成栅极，形成与源电接触的衬底接触，以及形成与源极的电接触， 漏极和栅极以及基板。

公开(公告)号：US07355221B2

公开(公告)日：2008-04-08

申请号：US10908448

申请日：2005-05-12

申请人： Gregory G. Freeman ,  Anil K. Chinthakindi ,  David R. Greenberg ,  Basanth Jagannathan ,  Marwan H. Khater ,  John Pekarik ,  Xudong Wang

发明人： Gregory G. Freeman ,  Anil K. Chinthakindi ,  David R. Greenberg ,  Basanth Jagannathan ,  Marwan H. Khater ,  John Pekarik ,  Xudong Wang

IPC分类号： H01L29/76

CPC分类号： H01L21/26586 ,  H01L21/26506 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/7843

摘要： A field effect transistor is provided which includes a contiguous single-crystal semiconductor region in which a source region, a channel region and a drain region are disposed. The channel region has an edge in common with the source region as a source edge, and the channel region further has an edge in common with the drain region as a drain edge. A gate conductor overlies the channel region. The field effect transistor further includes a structure which applies a stress at a first magnitude to only one of the source edge and the drain edge while applying the stress at no greater than a second magnitude to another one of the source edge and the drain edge, wherein the second magnitude has a value ranging from zero to about half the first magnitude. In a particular embodiment, the stress is applied at the first magnitude to the source edge while the zero or lower magnitude stress is applied to the drain edge. In another embodiment, the stress is applied at the first magnitude to the drain edge while the zero or lower magnitude stress is applied to the drain edge.

摘要翻译： 提供一种场效应晶体管，其包括其中设置有源极区，沟道区和漏极区的邻接单晶半导体区。 沟道区域具有与源极区域共同的边缘作为源极边缘，并且沟道区域还具有与作为漏极边缘的漏极区域共同的边缘。 栅极导体覆盖沟道区域。 场效应晶体管还包括将源极边缘和漏极边缘的另一个施加不大于第二幅度的应力的第一幅度的应力仅施加到源极边缘和漏极边缘中的一个的结构， 其中所述第二幅度具有从零到所述第一幅度的大约一半的值。 在特定实施例中，将应力以第一幅度施加到源极边缘，同时零或较小幅度应力施加到漏极边缘。 在另一个实施例中，将应力以第一幅度施加到漏极边缘，同时将零或较小的幅度应力施加到漏极边缘。

公开(公告)号：US06815802B2

公开(公告)日：2004-11-09

申请号：US10122857

申请日：2002-04-15

申请人： Jack Oon Chu ,  Douglass Duane Coolbaugh ,  James Stuart Dunn ,  David R. Greenberg ,  David L. Harame ,  Basanth Jagannathan ,  Robb Allen Johnson ,  Louis D. Lanzerotti ,  Kathryn Turner Schonenberg ,  Ryan Wayne Wuthrich

发明人： Jack Oon Chu ,  Douglass Duane Coolbaugh ,  James Stuart Dunn ,  David R. Greenberg ,  David L. Harame ,  Basanth Jagannathan ,  Robb Allen Johnson ,  Louis D. Lanzerotti ,  Kathryn Turner Schonenberg ,  Ryan Wayne Wuthrich

IPC分类号： H01L27082

CPC分类号： H01L29/66242 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L29/1004 ,  H01L29/161 ,  H01L29/7378

摘要： A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe base region formed on a portion of said collector region; and an emitter region of said first conductivity type formed over a portion of said base region, wherein said collector region and said base region include carbon continuously therein. The SiGe base region is further doped with boron.

公开(公告)号：US08829572B2

公开(公告)日：2014-09-09

申请号：US13398408

申请日：2012-02-16

申请人： Basanth Jagannathan ,  John J. Pekarik ,  Christopher M. Schnabel

发明人： Basanth Jagannathan ,  John J. Pekarik ,  Christopher M. Schnabel

IPC分类号： H01L29/66 ,  H01L27/088 ,  H01L21/70 ,  H01L23/552

CPC分类号： H01L29/78 ,  H01L23/4824 ,  H01L29/1087

摘要： Method of making a semiconductor device that includes forming a source and a drain in a substrate, forming a gate on the substrate between the source and drain, forming a substrate contact in electrical contact with the source, and forming an electrical contact to the source, drain and gate, and the substrate.

摘要翻译： 制造半导体器件的方法包括在衬底中形成源极和漏极，在源极和漏极之间的衬底上形成栅极，形成与源电接触的衬底接触，以及形成与源极的电接触， 漏极和栅极以及基板。

公开(公告)号：US07183576B2

公开(公告)日：2007-02-27

申请号：US10775514

申请日：2004-02-10

申请人： Jack Oon Chu ,  Basanth Jagannathan ,  Alfred Grill ,  Bernard Steele Meyerson ,  John Albrecht Ott

发明人： Jack Oon Chu ,  Basanth Jagannathan ,  Alfred Grill ,  Bernard Steele Meyerson ,  John Albrecht Ott

IPC分类号： H01L29/16 ,  H01L29/737

CPC分类号： C23C16/325 ,  C23C16/32 ,  C30B25/02 ,  C30B29/52 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02694 ,  Y10T428/12674

摘要： A method and apparatus for depositing single crystal, epitaxial films of silicon carbon and silicon germanium carbon on a plurality of substrates in a hot wall, isothermal UHV-CVD system is described. In particular, a multiple wafer low temperature growth technique in the range from 350° C. to 750° C. is described for incorporating carbon epitaxially in Si and SiGe films with very abrupt and well defined junctions, but without any associated oxygen background contamination. Preferably, these epitakial SiC and SiGeC films are in-situ doped p- or n-type and with the presence of low concentration of carbon

摘要翻译： 描述了一种用于在热壁，等温UHV-CVD系统中在多个基板上沉积单晶，硅碳和硅锗碳外延膜的方法和装置。 特别地，描述了在350℃至750℃的范围内的多晶片低温生长技术，用于在Si和SiGe膜中外延引入碳，其具有非常突然且明确限定的结，但没有任何相关的氧背景污染。 优选地，这些成膜SiC和SiGeC膜是原位掺杂的p型或n型，并且存在低浓度的碳<20 20 -3 -3， 生长的p型或n型掺杂物分布可以承受炉退火至850℃的温度和快速热退火温度至1000℃

公开(公告)号：US07173274B2

公开(公告)日：2007-02-06

申请号：US10953378

申请日：2004-09-29

申请人： Jack Oon Chu ,  Douglas Duane Coolbaugh ,  James Stuart Dunn ,  David R. Greenberg ,  David L. Harame ,  Basanth Jagannathan ,  Robb Allen Johnson ,  Louis D. Lanzerotti ,  Kathryn Turner Schonenberg ,  Ryan Wayne Wuthrich

发明人： Jack Oon Chu ,  Douglas Duane Coolbaugh ,  James Stuart Dunn ,  David R. Greenberg ,  David L. Harame ,  Basanth Jagannathan ,  Robb Allen Johnson ,  Louis D. Lanzerotti ,  Kathryn Turner Schonenberg ,  Ryan Wayne Wuthrich

IPC分类号： H01L29/06 ,  H01L31/072 ,  H01L31/109 ,  H01L31/0328 ,  H01L31/0339

CPC分类号： H01L29/66242 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L29/1004 ,  H01L29/161 ,  H01L29/7378

摘要： A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe base region formed on a portion of said collector region; and an emitter region of said first conductivity type formed over a portion of said base region, wherein said collector region and said base region include carbon continuously therein. The SiGe base region is further doped with boron.

摘要翻译： 提供了在发射极和集电极区域之间基本上不存在位错缺陷的SiGe双极晶体管及其形成方法。 SiGe双极晶体管包括第一导电类型的集电极区域; 形成在所述集电区域的一部分上的SiGe基区; 以及形成在所述基极区域的一部分上的所述第一导电类型的发射极区域，其中所述集电极区域和所述基极区域在其中连续地包括碳。 SiGe基区进一步掺硼。