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7 条记录 (耗时 0.026 秒)

    METHOD FOR FORMING CHIP PACKAGE
    2.
    发明申请
    METHOD FOR FORMING CHIP PACKAGE 有权
    形成芯片包装的方法

    公开(公告)号：US20120184070A1

    公开(公告)日：2012-07-19

    申请号：US13352234

    申请日：2012-01-17

    申请人： Chien-Hui CHEN ,  Ming-Kun YANG ,  Tsang-Yu LIU ,  Yen-Shih HO

    发明人： Chien-Hui CHEN ,  Ming-Kun YANG ,  Tsang-Yu LIU ,  Yen-Shih HO

    IPC分类号： H01L21/78

    CPC分类号： H01L21/76898 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/73253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00014 ,  H01L2924/00

    摘要： An embodiment of the invention provides a method for forming a chip package which includes: providing a substrate having a first surface and a second surface, wherein at least two conducting pads are disposed on the first surface of the substrate; partially removing the substrate from the second surface of the substrate to form at least two holes extending towards the first surface, wherein the holes correspondingly and respectively align with one of the conducting pads; after the holes are formed, partially removing the substrate from the second substrate to form at least a recess extending towards the first surface, wherein the recess overlaps with the holes; forming an insulating layer on a sidewall and a bottom of the trench and on sidewalls of the holes; and forming a conducting layer on the insulating layer, wherein the conducting layer electrically contacts with one of the conducting pads.

    摘要翻译： 本发明的一个实施例提供了一种用于形成芯片封装的方法，其包括：提供具有第一表面和第二表面的衬底，其中至少两个导电焊盘设置在衬底的第一表面上; 从衬底的第二表面部分地去除衬底以形成朝向第一表面延伸的至少两个孔，其中，孔对应并分别对准导电焊盘中的一个; 在形成所述孔之后，从所述第二基板部分地移除所述基板以形成朝向所述第一表面延伸的至少一个凹部，其中所述凹部与所述孔重叠; 在沟槽的侧壁和底部以及孔的侧壁上形成绝缘层; 以及在所述绝缘层上形成导电层，其中所述导电层与所述导电焊盘之一电接触。

    CHIP PACKAGE AND METHOD FOR FORMING THE SAME
    3.
    发明申请
    CHIP PACKAGE AND METHOD FOR FORMING THE SAME 有权
    芯片包装及其形成方法

    公开(公告)号：US20120319297A1

    公开(公告)日：2012-12-20

    申请号：US13524985

    申请日：2012-06-15

    申请人： Yu-Lin YEN ,  Chien-Hui CHEN ,  Tsang-Yu LIU ,  Yen-Shih HO

    发明人： Yu-Lin YEN ,  Chien-Hui CHEN ,  Tsang-Yu LIU ,  Yen-Shih HO

    IPC分类号： H01L23/48 ,  H01L21/78

    CPC分类号： H01L23/3128 ,  H01L23/3114 ,  H01L23/481 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2924/1461 ,  H01L2924/014 ,  H01L2924/00

    摘要： An embodiment of the invention provides a chip package which includes: a substrate having a plurality of sides and a plurality of corner regions, wherein each of the corner regions is located at an intersection of at least two of the sides of the substrate; a device region formed in the substrate; a conducting layer disposed on the substrate and electrically connected to the device region; an insulating layer disposed between the substrate and the conducting layer; and a carrier substrate, wherein the substrate is disposed on the carrier substrate, and the substrate has a recess extending towards the carrier substrate in at least one of the corner regions.

    摘要翻译： 本发明的实施例提供一种芯片封装，其包括：具有多个侧面和多个拐角区域的基板，其中每个所述拐角区域位于所述基板的至少两个侧面的相交处; 形成在所述基板中的器件区域; 导电层，其设置在所述基板上并电连接到所述器件区域; 设置在所述基板和所述导电层之间的绝缘层; 以及载体基板，其中所述基板设置在所述载体基板上，并且所述基板具有在至少一个所述拐角区域中朝向所述载体基板延伸的凹部。