公开(公告)号：US20120146108A1

公开(公告)日：2012-06-14

申请号：US13314122

申请日：2011-12-07

申请人： Shu-Ming CHANG ,  Chien-Hui CHEN ,  Yen-Shih HO ,  Chien-Hung LIU ,  Ho-Yin YIU ,  Ying-Nan WEN

发明人： Shu-Ming CHANG ,  Chien-Hui CHEN ,  Yen-Shih HO ,  Chien-Hung LIU ,  Ho-Yin YIU ,  Ying-Nan WEN

IPC分类号： H01L29/772 ,  H01L21/762

CPC分类号： H01L24/05 ,  H01L21/6835 ,  H01L21/76898 ,  H01L24/03 ,  H01L2221/6834 ,  H01L2221/6835 ,  H01L2221/68368 ,  H01L2224/0401 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2224/05552

摘要： An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and an opposite second surface; a drain region located in the semiconductor substrate; a source region located in the semiconductor substrate; a gate located on the semiconductor substrate or at least partially buried in the semiconductor substrate, wherein a gate dielectric layer is between the gate and the semiconductor substrate; a drain conducting structure disposed on the first surface of the semiconductor substrate and electrically connected to the drain region; a source conducting structure disposed on the second surface of the semiconductor substrate and electrically connected to the source region; and a gate conducting structure disposed on the first surface of the semiconductor substrate and electrically connected to the gate.

摘要翻译： 本发明的实施例提供一种芯片封装，其包括：具有第一表面和相对的第二表面的半导体衬底; 位于半导体衬底中的漏区; 源区域，位于所述半导体衬底中; 位于所述半导体衬底上或至少部分地埋设在所述半导体衬底中的栅极，其中栅极电介质层位于所述栅极和所述半导体衬底之间; 漏极导电结构，设置在所述半导体衬底的所述第一表面上并电连接到所述漏极区; 源极导电结构，其设置在所述半导体衬底的所述第二表面上并电连接到所述源极区; 以及栅极导电结构，其设置在所述半导体衬底的所述第一表面上并电连接到所述栅极。

公开(公告)号：US20120146153A1

公开(公告)日：2012-06-14

申请号：US13314114

申请日：2011-12-07

申请人： Ying-Nan WEN ,  Ho-Yin YIU ,  Yen-Shih HO ,  Shu-Ming CHANG ,  Chien-Hung LIU ,  Shih-Yi LEE ,  Wei-Chung YANG

发明人： Ying-Nan WEN ,  Ho-Yin YIU ,  Yen-Shih HO ,  Shu-Ming CHANG ,  Chien-Hung LIU ,  Shih-Yi LEE ,  Wei-Chung YANG

IPC分类号： H01L27/092 ,  H01L21/28 ,  H01L21/768

CPC分类号： H01L21/76898 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3185 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/6835 ,  H01L2221/68363 ,  H01L2224/02372 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05672 ,  H01L2224/11002 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/96 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2224/05552

摘要： A chip package includes: a substrate; a drain and a source regions located in the substrate; a gate located on or buried in the substrate; a drain conducting structure, a source conducting structure, and a gate conducting structure, disposed on the substrate and electrically connected to the drain region, the source region, and the gate, respectively; a second substrate disposed beside the substrate; a second drain and a second source region located in the second substrate, wherein the second drain region is electrically connected to the source region; a second gate located on or buried in the second substrate; and a second source and a second gate conducting structure disposed on the second substrate and electrically connected to the second source region and the second gate, respectively, wherein terminal points of the drain, the source, the gate, the second source, and the second gate conducting structures are substantially coplanar.

摘要翻译： 芯片封装包括：基板; 位于衬底中的漏极和源极区域; 位于衬底上或埋在衬底中的门; 漏极导电结构，源极导电结构和栅极导电结构，分别设置在所述衬底上并电连接到所述漏极区域，所述源极区域和所述栅极; 设置在所述基板旁边的第二基板; 位于所述第二基板中的第二漏极和第二源极区域，其中所述第二漏极区域电连接到所述源极区域; 位于第二基板上或埋在第二基板中的第二栅极; 以及第二源极和第二栅极导电结构，其设置在所述第二基板上并分别电连接到所述第二源极区域和所述第二栅极，其中所述漏极，所述源极，所述栅极，所述第二源极和所述第二栅极的端点 栅极导电结构基本上共面。

公开(公告)号：US20120194301A1

公开(公告)日：2012-08-02

申请号：US13359460

申请日：2012-01-26

申请人： Ho-Yin YIU ,  Chien-Hung LIU ,  Ying-Nan WEN ,  Shih-Yi LEE ,  Wei-Chung YANG ,  Bai-Yao LOU ,  Hung-Jen LEE

发明人： Ho-Yin YIU ,  Chien-Hung LIU ,  Ying-Nan WEN ,  Shih-Yi LEE ,  Wei-Chung YANG ,  Bai-Yao LOU ,  Hung-Jen LEE

IPC分类号： H03H7/00 ,  H01P5/02

CPC分类号： H01L23/642 ,  H01L23/48 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0655 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01327 ,  H01L2924/1901 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/014

摘要： Embodiments of the present invention provide a capacitive coupler packaging structure including a substrate with at least one capacitor and a receiver formed thereon, wherein the at least one capacitor at least includes a first electrode layer, a second electrode layer and a capacitor dielectric layer therebetween, and the first electrode layer is electrically connected to the receiver via a solder ball. The capacitive coupler packaging structure also includes a transmitter electrically connecting to the capacitor.

摘要翻译： 本发明的实施例提供一种电容耦合器封装结构，其包括具有至少一个电容器的基板和形成在其上的接收器，其中所述至少一个电容器至少包括第一电极层，第二电极层和电介质层之间， 并且第一电极层通过焊球电连接到接收器。 电容耦合器封装结构还包括电连接到电容器的发射器。

公开(公告)号：US20120194148A1

公开(公告)日：2012-08-02

申请号：US13359466

申请日：2012-01-26

申请人： Ho-Yin YIU ,  Bai-Yao LOU ,  Chien-Hung LIU ,  Wei-Chung YANG

发明人： Ho-Yin YIU ,  Bai-Yao LOU ,  Chien-Hung LIU ,  Wei-Chung YANG

IPC分类号： G05F1/10 ,  H01L21/50

CPC分类号： H02M3/155 ,  H01F17/0006 ,  H01F2017/0046 ,  H01F2017/0073 ,  H01F2017/0086 ,  H01L23/645 ,  H01L24/16 ,  H01L25/072 ,  H01L25/165 ,  H01L2224/16225 ,  H01L2924/13091 ,  H01L2924/16195 ,  H01L2924/19105 ,  H02M3/00

摘要： A power module includes a substrate; a conductive path layer formed on the substrate with a specific pattern as an inductor; a connection layer being formed on the substrate and electrically connected to a first terminal of the inductor; and a first transistor, electrically mounted on the substrate through the connection layer.

摘要翻译： 电源模块包括基板; 形成在具有特定图案的基板上的导电路径层作为电感器; 连接层形成在所述基板上并电连接到所述电感器的第一端子; 以及第一晶体管，通过连接层电安装在基板上。

公开(公告)号：US20120305977A1

公开(公告)日：2012-12-06

申请号：US13484140

申请日：2012-05-30

申请人： Ying-Nan WEN ,  Chien-Hung LIU ,  Wei-Chung YANG

发明人： Ying-Nan WEN ,  Chien-Hung LIU ,  Wei-Chung YANG

IPC分类号： H01L33/62 ,  H01L23/48 ,  H01L21/283

CPC分类号： H05K3/185 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/1461 ,  H01L2924/181 ,  H05K1/115 ,  H05K3/0023 ,  H05K3/426 ,  H05K2201/10378 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： An embodiment of the present invention provides a manufacturing method of an interposer including: providing a semiconductor substrate having a first surface, a second surface and at least a through hole connecting the first surface to the second surface; electrocoating a polymer layer on the first surface, the second surface and an inner wall of the through hole; and forming a wiring layer on the electrocoating polymer layer, wherein the wiring layer extends from the first surface to the second surface via the inner wall of the through hole. Another embodiment of the present invention provides an interposer.

摘要翻译： 本发明的一个实施例提供了一种内插器的制造方法，包括：提供具有第一表面，第二表面和至少连接第一表面与第二表面的通孔的半导体衬底; 在第一表面，第二表面和通孔的内壁上电聚合聚合物层; 以及在所述电涂层聚合物层上形成布线层，其中所述布线层经由所述通孔的内壁从所述第一表面延伸到所述第二表面。 本发明的另一实施例提供一种插入器。

公开(公告)号：US20110317371A1

公开(公告)日：2011-12-29

申请号：US12826251

申请日：2010-06-29

申请人： Chien-Hung LIU

发明人： Chien-Hung LIU

IPC分类号： H05K7/00 ,  H01L21/00

CPC分类号： H01L21/76898 ,  H01L21/6835 ,  H01L21/76831 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L24/93 ,  H01L24/95 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/50 ,  H01L27/14618 ,  H01L2221/68327 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/05551 ,  H01L2224/0557 ,  H01L2224/1132 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/2405 ,  H01L2224/241 ,  H01L2224/24145 ,  H01L2224/24146 ,  H01L2224/24226 ,  H01L2224/245 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32147 ,  H01L2224/32155 ,  H01L2224/83005 ,  H01L2224/83203 ,  H01L2224/83805 ,  H01L2224/8385 ,  H01L2224/8389 ,  H01L2224/83893 ,  H01L2224/9202 ,  H01L2224/92144 ,  H01L2224/93 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2225/1011 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/141 ,  H01L2924/143 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2224/82 ,  H01L2224/11 ,  H01L2224/05552 ,  H01L2924/00

摘要： An electronic component package is described. The electronic component package includes a first electronic component package module mounted on a surface of a packaging layer. A second electronic component package module laminated on a bottom of the first electronic component package module is mounted on a surface of a packaging layer. The first and second electronic component package modules respectively include at least two semiconductor chips laminated. A first redistribution layer is between the first and the second electronic component package modules, electrically connected to the first and the second electronic component package modules. A conductive bump is mounted on a bottom of the second electronic component package module, electrically connected to the second electronic component package module.

摘要翻译： 描述电子部件包装。 电子部件封装包括安装在包装层的表面上的第一电子部件封装模块。 层叠在第一电子部件封装模块的底部上的第二电子部件封装模块安装在包装层的表面上。 第一和第二电子部件封装模块分别包括层叠的至少两个半导体芯片。 第一再分配层位于第一和第二电子部件封装模块之间，电连接到第一和第二电子部件封装模块。 导电凸块安装在第二电子部件封装模块的底部，电连接到第二电子部件封装模块。

公开(公告)号：US20110079903A1

公开(公告)日：2011-04-07

申请号：US12899258

申请日：2010-10-06

申请人： Chien-Hung LIU

发明人： Chien-Hung LIU

IPC分类号： H01L23/498 ,  H01L21/78

CPC分类号： H01L24/03 ,  H01L21/6835 ,  H01L24/32 ,  H01L2221/68372 ,  H01L2224/0236 ,  H01L2224/02377 ,  H01L2224/02381 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/11849 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00

摘要： A chip package and a fabrication method thereof are provided. The chip package includes a semiconductor substrate containing a semiconductor component and a conductive pad thereon. A through hole penetrates the semiconductor substrate from a backside thereof to expose the conductive pad. A redistribution layer is below the backside of the semiconductor substrate and electrically connected to the conductive pad in the through hole. A conductive trace layer is below the redistribution layer and extended along a sidewall of the semiconductor substrate to electrically contact with an edge of the redistribution layer.

摘要翻译： 提供了芯片封装及其制造方法。 芯片封装包括其上包含半导体部件和导电焊盘的半导体衬底。 通孔从其背面穿透半导体衬底以露出导电焊盘。 再分配层位于半导体衬底的背面下方并且与通孔中的导电焊盘电连接。 导电迹线层位于再分布层之下并且沿着半导体衬底的侧壁延伸以与再分布层的边缘电接触。

公开(公告)号：US20130138837A1

公开(公告)日：2013-05-30

申请号：US13444315

申请日：2012-04-11

申请人： Chien-Hung LIU

发明人： Chien-Hung LIU

IPC分类号： G06F3/00

CPC分类号： G06F3/0607 ,  G06F3/0661 ,  G06F3/0676

摘要： An accessing device communicating with a host device and including a connector, a storage unit and a control unit is disclosed. The connector connects to the host device. The storage unit stores data. The control unit communicates with the storage unit according to a first communication protocol and communicates with the host device via the connector according to a second communication protocol. The control unit determines the kind of the second communication protocol according to selection information.

摘要翻译： 公开了一种与主机设备通信并包括连接器，存储单元和控制单元的访问设备。 连接器连接到主机设备。 存储单元存储数据。 控制单元根据第一通信协议与存储单元通信，并根据第二通信协议经由连接器与主机设备进行通信。 控制单元根据选择信息确定第二通信协议的种类。

公开(公告)号：US20110297413A1

公开(公告)日：2011-12-08

申请号：US12860941

申请日：2010-08-23

申请人： Chien-Hung LIU ,  Po-Chuan HSIEH ,  YU-CHANG PAI

发明人： Chien-Hung LIU ,  Po-Chuan HSIEH ,  YU-CHANG PAI

IPC分类号： H05K7/00 ,  B23P19/04 ,  B23P17/00

CPC分类号： H05K9/0041 ,  B21D28/10 ,  Y10T29/49 ,  Y10T29/49826

摘要： An enclosure of an electronic device includes a plate. The plate defines a number of through holes. Each through hole has a pair of tabs connected to each other and with the through hole. Each pair of tabs are slantingly bent towards an inside of the enclosure. The enclosure with the shields can shield the electronic device from electro-magnetic interference.

摘要翻译： 电子设备的外壳包括板。 该板限定了多个通孔。 每个通孔具有彼此连接并与通孔连接的一对突片。 每对翼片朝向机壳的内侧倾斜弯曲。 带屏蔽的外壳可以屏蔽电子设备免受电磁干扰。

公开(公告)号：US20110213490A1

公开(公告)日：2011-09-01

申请号：US12713181

申请日：2010-02-26

申请人： Chien-Hung LIU ,  Wen-Yuh JYWE ,  Yi-Tsung LI

发明人： Chien-Hung LIU ,  Wen-Yuh JYWE ,  Yi-Tsung LI

IPC分类号： G05B19/404 ,  G05B19/402

CPC分类号： G05B19/401 ,  B23Q1/5437 ,  B23Q17/2233 ,  B23Q17/2495 ,  G01B11/03 ,  G01B11/27 ,  G01B21/045 ,  G05B2219/37008 ,  G05B2219/37275 ,  Y10T409/305824

摘要： A method of detecting a dynamic path of a five-axis machine tool having a spindle and a turntable and has a preparing step, a correcting step and a detecting step. The preparing step includes mounting a detector on the spindle, mounting a cat-eye reflector on the turntable, emitting a laser light to the cat-eye reflector, reflecting the laser light to the detector and splitting into two light beams. One of the light beams is emitted to a four-quadrant position sensitive detector. The correcting step includes rotating the detector, detecting a signal of the laser light by the four-quadrant position sensitive detector to eliminate an offset between the detecting assembly and the spindle. The detecting step includes detecting the dynamic path of the five-axis machine tool by detecting the positions of at least two of the linear axes and at least one of the rotation axes of the five-axis machine tool.

摘要翻译： 一种检测具有主轴和转盘的五轴机床的动态路径的方法，具有准备步骤，校正步骤和检测步骤。 制备步骤包括将检测器安装在心轴上，将猫眼反射器安装在转盘上，向猫眼反射器发射激光，将激光反射到检测器并分成两束光束。 一个光束被发射到四象限位置敏感检测器。 校正步骤包括旋转检测器，通过四象限位置敏感检测器检测激光的信号，以消除检测组件和主轴之间的偏移。 检测步骤包括通过检测五轴机床的至少两个线性轴线和至少一个旋转轴线的位置来检测五轴机床的动态路径。