公开(公告)号：US20120146108A1

公开(公告)日：2012-06-14

申请号：US13314122

申请日：2011-12-07

申请人： Shu-Ming CHANG ,  Chien-Hui CHEN ,  Yen-Shih HO ,  Chien-Hung LIU ,  Ho-Yin YIU ,  Ying-Nan WEN

发明人： Shu-Ming CHANG ,  Chien-Hui CHEN ,  Yen-Shih HO ,  Chien-Hung LIU ,  Ho-Yin YIU ,  Ying-Nan WEN

IPC分类号： H01L29/772 ,  H01L21/762

CPC分类号： H01L24/05 ,  H01L21/6835 ,  H01L21/76898 ,  H01L24/03 ,  H01L2221/6834 ,  H01L2221/6835 ,  H01L2221/68368 ,  H01L2224/0401 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2224/05552

摘要： An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and an opposite second surface; a drain region located in the semiconductor substrate; a source region located in the semiconductor substrate; a gate located on the semiconductor substrate or at least partially buried in the semiconductor substrate, wherein a gate dielectric layer is between the gate and the semiconductor substrate; a drain conducting structure disposed on the first surface of the semiconductor substrate and electrically connected to the drain region; a source conducting structure disposed on the second surface of the semiconductor substrate and electrically connected to the source region; and a gate conducting structure disposed on the first surface of the semiconductor substrate and electrically connected to the gate.

摘要翻译： 本发明的实施例提供一种芯片封装，其包括：具有第一表面和相对的第二表面的半导体衬底; 位于半导体衬底中的漏区; 源区域，位于所述半导体衬底中; 位于所述半导体衬底上或至少部分地埋设在所述半导体衬底中的栅极，其中栅极电介质层位于所述栅极和所述半导体衬底之间; 漏极导电结构，设置在所述半导体衬底的所述第一表面上并电连接到所述漏极区; 源极导电结构，其设置在所述半导体衬底的所述第二表面上并电连接到所述源极区; 以及栅极导电结构，其设置在所述半导体衬底的所述第一表面上并电连接到所述栅极。

公开(公告)号：US20120146153A1

公开(公告)日：2012-06-14

申请号：US13314114

申请日：2011-12-07

申请人： Ying-Nan WEN ,  Ho-Yin YIU ,  Yen-Shih HO ,  Shu-Ming CHANG ,  Chien-Hung LIU ,  Shih-Yi LEE ,  Wei-Chung YANG

发明人： Ying-Nan WEN ,  Ho-Yin YIU ,  Yen-Shih HO ,  Shu-Ming CHANG ,  Chien-Hung LIU ,  Shih-Yi LEE ,  Wei-Chung YANG

IPC分类号： H01L27/092 ,  H01L21/28 ,  H01L21/768

CPC分类号： H01L21/76898 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3185 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/6835 ,  H01L2221/68363 ,  H01L2224/02372 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05672 ,  H01L2224/11002 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/96 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2224/05552

摘要： A chip package includes: a substrate; a drain and a source regions located in the substrate; a gate located on or buried in the substrate; a drain conducting structure, a source conducting structure, and a gate conducting structure, disposed on the substrate and electrically connected to the drain region, the source region, and the gate, respectively; a second substrate disposed beside the substrate; a second drain and a second source region located in the second substrate, wherein the second drain region is electrically connected to the source region; a second gate located on or buried in the second substrate; and a second source and a second gate conducting structure disposed on the second substrate and electrically connected to the second source region and the second gate, respectively, wherein terminal points of the drain, the source, the gate, the second source, and the second gate conducting structures are substantially coplanar.

摘要翻译： 芯片封装包括：基板; 位于衬底中的漏极和源极区域; 位于衬底上或埋在衬底中的门; 漏极导电结构，源极导电结构和栅极导电结构，分别设置在所述衬底上并电连接到所述漏极区域，所述源极区域和所述栅极; 设置在所述基板旁边的第二基板; 位于所述第二基板中的第二漏极和第二源极区域，其中所述第二漏极区域电连接到所述源极区域; 位于第二基板上或埋在第二基板中的第二栅极; 以及第二源极和第二栅极导电结构，其设置在所述第二基板上并分别电连接到所述第二源极区域和所述第二栅极，其中所述漏极，所述源极，所述栅极，所述第二源极和所述第二栅极的端点 栅极导电结构基本上共面。

公开(公告)号：US20120194301A1

公开(公告)日：2012-08-02

申请号：US13359460

申请日：2012-01-26

申请人： Ho-Yin YIU ,  Chien-Hung LIU ,  Ying-Nan WEN ,  Shih-Yi LEE ,  Wei-Chung YANG ,  Bai-Yao LOU ,  Hung-Jen LEE

发明人： Ho-Yin YIU ,  Chien-Hung LIU ,  Ying-Nan WEN ,  Shih-Yi LEE ,  Wei-Chung YANG ,  Bai-Yao LOU ,  Hung-Jen LEE

IPC分类号： H03H7/00 ,  H01P5/02

CPC分类号： H01L23/642 ,  H01L23/48 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0655 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01327 ,  H01L2924/1901 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/014

摘要： Embodiments of the present invention provide a capacitive coupler packaging structure including a substrate with at least one capacitor and a receiver formed thereon, wherein the at least one capacitor at least includes a first electrode layer, a second electrode layer and a capacitor dielectric layer therebetween, and the first electrode layer is electrically connected to the receiver via a solder ball. The capacitive coupler packaging structure also includes a transmitter electrically connecting to the capacitor.

摘要翻译： 本发明的实施例提供一种电容耦合器封装结构，其包括具有至少一个电容器的基板和形成在其上的接收器，其中所述至少一个电容器至少包括第一电极层，第二电极层和电介质层之间， 并且第一电极层通过焊球电连接到接收器。 电容耦合器封装结构还包括电连接到电容器的发射器。

公开(公告)号：US20120146111A1

公开(公告)日：2012-06-14

申请号：US13324815

申请日：2011-12-13

申请人： Shu-Ming CHANG ,  Yen-Shih HO ,  Ho-Yin YIU

发明人： Shu-Ming CHANG ,  Yen-Shih HO ,  Ho-Yin YIU

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/76898 ,  H01L2924/0002 ,  H01L2924/13091 ,  H01L2924/157 ,  H01L2924/00

摘要： An embodiment of the invention provides a chip package including a semiconductor substrate, a drain electrode, a source electrode and a gate electrode. The semiconductor substrate has a first surface and an opposite second surface wherein the second surface has a recess. The drain electrode is disposed on the first surface and covers the recess. The source electrode is disposed on the second surface in a position corresponding to the drain electrode covering the recess. The gate electrode is disposed on the second surface. An embodiment of the invention further provides a manufacturing method of a chip package.

摘要翻译： 本发明的实施例提供一种包括半导体衬底，漏电极，源电极和栅电极的芯片封装。 半导体衬底具有第一表面和相对的第二表面，其中第二表面具有凹部。 漏电极设置在第一表面上并覆盖凹部。 源电极设置在与覆盖凹部的漏电极对应的位置的第二表面上。 栅电极设置在第二表面上。 本发明的实施例还提供了一种芯片封装的制造方法。

公开(公告)号：US20120194148A1

公开(公告)日：2012-08-02

申请号：US13359466

申请日：2012-01-26

申请人： Ho-Yin YIU ,  Bai-Yao LOU ,  Chien-Hung LIU ,  Wei-Chung YANG

发明人： Ho-Yin YIU ,  Bai-Yao LOU ,  Chien-Hung LIU ,  Wei-Chung YANG

IPC分类号： G05F1/10 ,  H01L21/50

CPC分类号： H02M3/155 ,  H01F17/0006 ,  H01F2017/0046 ,  H01F2017/0073 ,  H01F2017/0086 ,  H01L23/645 ,  H01L24/16 ,  H01L25/072 ,  H01L25/165 ,  H01L2224/16225 ,  H01L2924/13091 ,  H01L2924/16195 ,  H01L2924/19105 ,  H02M3/00

摘要： A power module includes a substrate; a conductive path layer formed on the substrate with a specific pattern as an inductor; a connection layer being formed on the substrate and electrically connected to a first terminal of the inductor; and a first transistor, electrically mounted on the substrate through the connection layer.

摘要翻译： 电源模块包括基板; 形成在具有特定图案的基板上的导电路径层作为电感器; 连接层形成在所述基板上并电连接到所述电感器的第一端子; 以及第一晶体管，通过连接层电安装在基板上。