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1.发明授权Method of forming a substrate core with embedded capacitor and structures formed thereby 有权用嵌入式电容器形成衬底芯的方法和由此形成的结构公开(公告)号：US09572258B2
公开(公告)日：2017-02-14
申请号：US11027386
申请日：2004-12-30
申请人： Sriram Srinivasan , John S. Guzek , Cengiz A. Palanduz , Victor Prokofiev , Joel A. Auernheimer
发明人： Sriram Srinivasan , John S. Guzek , Cengiz A. Palanduz , Victor Prokofiev , Joel A. Auernheimer
CPC分类号： H05K1/162 , H01G4/10 , H01G4/1209 , H01G4/33 , H05K3/429 , H05K3/4611 , H05K2201/0175 , H05K2201/0179 , H05K2201/09309 , Y10T29/43 , Y10T29/49147 , Y10T29/49155 , Y10T29/49165
摘要： Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a substrate core by attaching a first dielectric layer to a second conductive layer of a thin film capacitor, and attaching a second dielectric layer to a first conductive layer of the thin film capacitor.
摘要翻译： 描述形成微电子结构的方法。 这些方法的实施例包括通过将第一电介质层附着到薄膜电容器的第二导电层并且将第二电介质层附接到薄膜电容器的第一导电层来形成衬底芯。
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2.发明授权Forming a substrate core with embedded capacitor and structures formed thereby 有权形成具有嵌入式电容器的基板芯和由此形成的结构公开(公告)号：US07224571B2
公开(公告)日：2007-05-29
申请号：US11218357
申请日：2005-09-02
申请人： Sriram Srinivasan , John S. Guzek , Cengiz A. Palanduz , Victor Prokofiev , Joel A. Auernheimer
发明人： Sriram Srinivasan , John S. Guzek , Cengiz A. Palanduz , Victor Prokofiev , Joel A. Auernheimer
IPC分类号： H01G4/228
CPC分类号： H05K1/162 , H01G4/10 , H01G4/1209 , H01G4/33 , H05K3/429 , H05K3/4611 , H05K2201/0175 , H05K2201/0179 , H05K2201/09309 , Y10T29/43 , Y10T29/49147 , Y10T29/49155 , Y10T29/49165
摘要： Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a substrate core by attaching a first dielectric layer to a second conductive layer of a thin film capacitor, and attaching a second dielectric layer to a first conductive layer of the thin film capacitor.
摘要翻译： 描述形成微电子结构的方法。 这些方法的实施例包括通过将第一电介质层附着到薄膜电容器的第二导电层并且将第二电介质层附接到薄膜电容器的第一导电层来形成衬底芯。
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3.发明授权Organic substrates with embedded thin-film capacitors, methods of making same, and systems containing same 有权具有嵌入式薄膜电容器的有机基板，其制造方法以及包含其的系统公开(公告)号：US07372126B2
公开(公告)日：2008-05-13
申请号：US11096235
申请日：2005-03-31
IPC分类号： H01L29/00
CPC分类号： H01L23/49822 , H01G4/236 , H01G4/33 , H01L21/4857 , H01L23/50 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/16 , H01L2924/00014 , H01L2924/01019 , H01L2924/01046 , H01L2924/01078 , H01L2924/15312 , H05K1/162 , H05K2201/09309 , H05K2201/09481 , H05K2201/09509 , H05K2201/09518 , H05K2201/09718 , Y10T29/435 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A thin-film capacitor assembly includes two plates that are accessed through deep and shallow vias. The thin-film capacitor assembly is able to be coupled with a spacer and an interposer. The thin-film capacitor assembly is also able to be stacked with a plurality of thin-film capacitor assemblies. The thin-film capacitor assembly is also part of computing system.
摘要翻译： 薄膜电容器组件包括通过深和浅通孔访问的两个板。 薄膜电容器组件能够与间隔件和插入件耦合。 薄膜电容器组件也能够与多个薄膜电容器组件堆叠。 薄膜电容器组件也是计算系统的一部分。
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4.发明授权Organic substrates with embedded thin-film capacitors, methods of making same, and systems containing same 有权具有嵌入式薄膜电容器的有机基板，其制造方法以及包含其的系统公开(公告)号：US07636231B2
公开(公告)日：2009-12-22
申请号：US12055467
申请日：2008-03-26
IPC分类号： H01G4/06
CPC分类号： H01L23/49822 , H01G4/236 , H01G4/33 , H01L21/4857 , H01L23/50 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/16 , H01L2924/00014 , H01L2924/01019 , H01L2924/01046 , H01L2924/01078 , H01L2924/15312 , H05K1/162 , H05K2201/09309 , H05K2201/09481 , H05K2201/09509 , H05K2201/09518 , H05K2201/09718 , Y10T29/435 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A thin-film capacitor assembly includes two plates that are accessed through deep and shallow vias. The thin-film capacitor assembly is able to be coupled with a spacer and an interposer. The thin-film capacitor assembly is also able to be stacked with a plurality of thin-film capacitor assemblies. The thin-film capacitor assembly is also part of computing system.
摘要翻译： 薄膜电容器组件包括通过深和浅通孔访问的两个板。 薄膜电容器组件能够与间隔件和插入件耦合。 薄膜电容器组件也能够与多个薄膜电容器组件堆叠。 薄膜电容器组件也是计算系统的一部分。
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5.发明申请ORGANIC SUBSTRATES WITH EMBEDDED THIN-FILM CAPACITORS, METHODS OF MAKING SAME, AND SYSTEMS CONTAINING SAME 有权具有嵌入式薄膜电容器的有机基板，其制造方法和包含其的系统公开(公告)号：US20080174938A1
公开(公告)日：2008-07-24
申请号：US12055467
申请日：2008-03-26
CPC分类号： H01L23/49822 , H01G4/236 , H01G4/33 , H01L21/4857 , H01L23/50 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/16 , H01L2924/00014 , H01L2924/01019 , H01L2924/01046 , H01L2924/01078 , H01L2924/15312 , H05K1/162 , H05K2201/09309 , H05K2201/09481 , H05K2201/09509 , H05K2201/09518 , H05K2201/09718 , Y10T29/435 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A thin-film capacitor assembly includes two plates that are accessed through deep and shallow vias. The thin-film capacitor assembly is able to be coupled with a spacer and an interposer. The thin-film capacitor assembly is also able to be stacked with a plurality of thin-film capacitor assemblies. The thin-film capacitor assembly is also part of computing system.
摘要翻译： 薄膜电容器组件包括通过深和浅通孔访问的两个板。 薄膜电容器组件能够与间隔件和插入件耦合。 薄膜电容器组件也能够与多个薄膜电容器组件堆叠。 薄膜电容器组件也是计算系统的一部分。
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6.发明授权Organic substrates with integral thin-film capacitors, methods of making same, and systems containing same 有权具有集成薄膜电容器的有机衬底，其制造方法以及含有它们的系统公开(公告)号：US07288459B2
公开(公告)日：2007-10-30
申请号：US11095917
申请日：2005-03-31
申请人： John S. Guzek , Victor Prokofiev
发明人： John S. Guzek , Victor Prokofiev
IPC分类号： H01L21/20
CPC分类号： H05K1/162 , H01G4/236 , H01G4/33 , H01L21/4857 , H01L23/49822 , H01L23/50 , H01L23/642 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2224/16235 , H01L2924/00014 , H01L2924/01019 , H01L2924/01046 , H01L2924/01078 , H01L2924/15311 , H01L2924/15312 , H05K1/141 , H05K3/4602 , H05K2201/09309 , H05K2201/09481 , H05K2201/09518 , H05K2201/09718 , H05K2201/10674 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： An organic substrate, thin-film capacitor composite includes two plates that are accessed through deep and shallow vias. The organic substrate, thin-film capacitor composite includes integral structure with at least one trace in the organic substrate. The composite is able to be coupled with an interposer. The composite is also part of computing system.
摘要翻译： 有机基板，薄膜电容器复合材料包括通过深和浅通孔访问的两个板。 有机衬底，薄膜电容器复合材料包括在有机衬底中具有至少一个迹线的整体结构。 复合材料能够与插入件耦合。 复合也是计算系统的一部分。
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公开(公告)号：US09526285B2
公开(公告)日：2016-12-27
申请号：US13717909
申请日：2012-12-18
申请人： Aleksandar Aleksov , Ravindranath V. Mahajan , Sairam Agraharam , Ian A. Young , John C. Johnson , Debendra Mallik , John S. Guzek
发明人： Aleksandar Aleksov , Ravindranath V. Mahajan , Sairam Agraharam , Ian A. Young , John C. Johnson , Debendra Mallik , John S. Guzek
CPC分类号： A41D31/00 , H05K1/0274 , H05K1/038 , H05K1/188 , H05K3/323 , H05K3/3436 , Y10T29/4913
摘要： A flexible computing fabric and a method of forming thereof. The flexible computing fabric includes an electronic substrate including one or more channels and including at least two ends. At least one computational element is mounted on the electronic substrate between the two ends and at least one functional element is mounted on the electronic substrate between the two ends. The channels form an interconnect between the elements. In addition, the electronic substrate is flexible and exhibits a flexural modulus in the range of 0.1 GPa to 30 GPa.
摘要翻译： 一种灵活的计算结构及其形成方法。 柔性计算结构包括包括一个或多个通道并且包括至少两个端部的电子基板。 至少一个计算元件安装在两端之间的电子基板上，并且至少一个功能元件安装在两端之间的电子基板上。 通道形成元件之间的互连。 此外，电子基板是柔性的并且具有在0.1GPa至30GPa范围内的挠曲模量。
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8.发明授权Packaged semiconductor die with bumpless die-package interface for bumpless build-up layer (BBUL) packages 有权封装的半导体芯片，具有无冲击积层（BBUL）封装的无冲击模封装接口公开(公告)号：US09224674B2
公开(公告)日：2015-12-29
申请号：US13996495
申请日：2011-12-15
IPC分类号： H01L27/08 , H01L23/552 , H01L23/48 , H01L23/00
CPC分类号： H01L24/09 , H01L23/481 , H01L23/5384 , H01L23/5386 , H01L23/552 , H01L24/19 , H01L24/97 , H01L27/08 , H01L2224/04105 , H01L2224/08235 , H01L2224/32245 , H01L2224/73267 , H01L2224/97 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/1433 , H01L2924/1434 , H01L2924/15153 , H01L2924/00 , H01L2224/83 , H01L2224/82
摘要： A packaged semiconductor die with a bumpless die-package interface and methods of fabrication are described. For example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines, one of which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate. In another example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines with a layer of conductive vias disposed thereon. At least one of the conductive lines is coupled directly to a conductive via of the semiconductor die which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate.
摘要翻译： 描述了具有无冲击的模具 - 封装接口和制造方法的封装的半导体管芯。 例如，半导体封装包括具有最外层导电通孔的焊盘侧的衬底。 半导体管芯被嵌入在衬底中并且具有最上层的导电线，其中之一直接连接到衬底的导电通孔的最下层的导电通孔。 在另一示例中，半导体封装包括具有最外层导电通孔的焊盘侧的衬底。 半导体管芯被嵌入在衬底中，并且具有最上层的导电线，其上设置有导电通孔层。 导电线中的至少一个直接耦合到半导体管芯的导电通孔，该导电通孔直接连接到衬底的导电通路的最下层的导电通孔。
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公开(公告)号：US20150171065A1
公开(公告)日：2015-06-18
申请号：US14104877
申请日：2013-12-12
CPC分类号： H01L25/18 , H01L23/3128 , H01L23/3675 , H01L23/481 , H01L23/49816 , H01L23/5384 , H01L23/5389 , H01L24/17 , H01L24/19 , H01L24/20 , H01L25/0652 , H01L25/50 , H01L2224/12105 , H01L2224/16145 , H01L2224/16225 , H01L2224/16235 , H01L2224/2518 , H01L2224/73253 , H01L2224/73259 , H01L2225/06513 , H01L2225/06517 , H01L2225/06548 , H01L2225/06562 , H01L2225/06589 , H01L2924/1205 , H01L2924/1206 , H01L2924/1427 , H01L2924/1432 , H01L2924/1434 , H01L2924/15321 , H01L2924/16251 , H01L2924/182
摘要： Embodiment of the present disclosure describe integrated circuit package assemblies that allow for relatively short connections between devices such as a processor and memory. In one embodiment, a package assembly includes a die embedded in a subpackage directly coupled to another die attached to the subpackage. In some embodiments the subpackage may also contain power management devices. In some embodiments the die embedded in the subpackage and/or the power management device may overlap, or be located in, a region defined by the die coupled to the subpackage such that they are located between the die coupled to the subpackage and a substrate underlying the subpackage. Other embodiments may be described and/or claimed.
摘要翻译： 本公开的实施例描述了允许诸如处理器和存储器的设备之间的相对短的连接的集成电路封装组件。 在一个实施例中，封装组件包括嵌入到直接耦合到附接到子封装的另一管芯的子封装中的管芯。 在一些实施例中，子包还可以包含电源管理装置。 在一些实施例中，嵌入在子封装和/或功率管理器件中的管芯可以与耦合到子封装的管芯定义的区域重叠或位于其中，使得它们位于耦合到子封装的管芯和衬底之间 子包。 可以描述和/或要求保护其他实施例。
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公开(公告)号：US20110101516A1
公开(公告)日：2011-05-05
申请号：US12590138
申请日：2009-11-03
CPC分类号： H01L23/49833 , H01L22/14 , H01L22/20 , H01L2224/16225 , H01L2224/16227 , H01L2924/00014 , H01L2924/15311 , H01L2224/0401
摘要： A microelectronic package includes a first substrate (120) having a first surface area (125) and a second substrate (130) having a second surface area (135). The first substrate includes a first set of interconnects (126) having a first pitch (127) at a first surface (121) and a second set of interconnects (128) having a second pitch (129) at a second surface (222). The second substrate is coupled to the first substrate using the second set of interconnects and includes a third set of interconnects (236) having a third pitch (237) and internal electrically conductive layers (233, 234) connected to each other with a microvia (240). The first pitch is smaller than the second pitch, the second pitch is smaller than the third pitch, and the first surface area is smaller than the second surface area.
摘要翻译： 微电子封装包括具有第一表面区域（125）的第一衬底（120）和具有第二表面区域（135）的第二衬底（130）。 第一衬底包括在第一表面处具有第一间距（127）的第一组互连（126）和在第二表面（222）处具有第二间距（129）的第二组互连（128）。 第二衬底使用第二组互连件耦合到第一衬底，并且包括具有第三间距（237）和第三组互连（236）的第三组互连（236），并且内部导电层（233,234）以微孔（ 240）。 第一间距小于第二间距，第二间距小于第三间距，第一表面积小于第二表面积。
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