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    Methods of forming an interconnect between a substrate bit line contact and a bit line in DRAM
    1.
    发明授权
    Methods of forming an interconnect between a substrate bit line contact and a bit line in DRAM 有权
    在DRAM中形成衬底位线接触和位线之间的互连的方法

    公开(公告)号：US08691656B2

    公开(公告)日：2014-04-08

    申请号：US13226787

    申请日：2011-09-07

    申请人： Brett W. Busch ,  David K. Hwang ,  F. Daniel Gealy

    发明人： Brett W. Busch ,  David K. Hwang ,  F. Daniel Gealy

    IPC分类号： H01L21/8242

    CPC分类号： H01L21/76879 ,  B82Y10/00 ,  H01L21/28525 ,  H01L21/76885 ,  H01L21/76897 ,  H01L27/10811 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10888 ,  H01L28/91 ,  Y10S977/773

    摘要： The invention includes methods of electrically interconnecting different elevation conductive structures, methods of forming capacitors, methods of forming an interconnect between a substrate bit line contact and a bit line in DRAM, and methods of forming DRAM memory cells. In one implementation, a method of electrically interconnecting different elevation conductive structures includes forming a first conductive structure comprising a first electrically conductive surface at a first elevation of a substrate. A nanowhisker is grown from the first electrically conductive surface, and is provided to be electrically conductive. Electrically insulative material is provided about the nanowhisker. An electrically conductive material is deposited over the electrically insulative material in electrical contact with the nanowhisker at a second elevation which is elevationally outward of the first elevation, and the electrically conductive material is provided into a second conductive structure. Other aspects and implementations are contemplated.

    摘要翻译： 本发明包括电互连不同高程导电结构的方法，形成电容器的方法，在DRAM中形成衬底位线接触和位线之间的互连的方法，以及形成DRAM存储单元的方法。 在一个实施方式中，电连接不同高程导电结构的方法包括在衬底的第一高度处形成包括第一导电表面的第一导电结构。 纳米晶须从第一导电表面生长，并被提供为导电的。 提供关于纳米晶须的电绝缘材料。 导电材料沉积在电绝缘材料上，在第二高度处与纳米晶须电接触，第二高度位于第一高度的正上方，并且导电材料被提供到第二导电结构中。 考虑了其他方面和实现。

    Methods Of Forming An Interconnect Between A Substrate Bit Line Contact And A Bit Line In DRAM
    2.
    发明申请
    Methods Of Forming An Interconnect Between A Substrate Bit Line Contact And A Bit Line In DRAM 有权
    在DRAM中形成基板位线触点和位线之间的互连的方法

    公开(公告)号：US20110318921A1

    公开(公告)日：2011-12-29

    申请号：US13226787

    申请日：2011-09-07

    申请人： Brett W. Busch ,  David K. Hwang ,  F. Daniel Gealy

    发明人： Brett W. Busch ,  David K. Hwang ,  F. Daniel Gealy

    IPC分类号： H01L21/28 ,  B82Y40/00

    CPC分类号： H01L21/76879 ,  B82Y10/00 ,  H01L21/28525 ,  H01L21/76885 ,  H01L21/76897 ,  H01L27/10811 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10888 ,  H01L28/91 ,  Y10S977/773

    摘要： The invention includes methods of electrically interconnecting different elevation conductive structures, methods of forming capacitors, methods of forming an interconnect between a substrate bit line contact and a bit line in DRAM, and methods of forming DRAM memory cells. In one implementation, a method of electrically interconnecting different elevation conductive structures includes forming a first conductive structure comprising a first electrically conductive surface at a first elevation of a substrate. A nanowhisker is grown from the first electrically conductive surface, and is provided to be electrically conductive. Electrically insulative material is provided about the nanowhisker. An electrically conductive material is deposited over the electrically insulative material in electrical contact with the nanowhisker at a second elevation which is elevationally outward of the first elevation, and the electrically conductive material is provided into a second conductive structure. Other aspects and implementations are contemplated.

    摘要翻译： 本发明包括电互连不同高程导电结构的方法，形成电容器的方法，在DRAM中形成衬底位线接触和位线之间的互连的方法，以及形成DRAM存储单元的方法。 在一个实施方式中，电连接不同高程导电结构的方法包括在衬底的第一高度处形成包括第一导电表面的第一导电结构。 纳米晶须从第一导电表面生长，并被提供为导电的。 提供关于纳米晶须的电绝缘材料。 导电材料沉积在电绝缘材料上，在第二高度处与纳米晶须电接触，第二高度位于第一高度的正上方，并且导电材料被提供到第二导电结构中。 考虑了其他方面和实现。

    Methods Of Forming An Interconnect Between A Substrate Bit Line Contact And A Bit Line In DRAM, And Methods Of Forming DRAM Memory Cells
    3.
    发明申请
    Methods Of Forming An Interconnect Between A Substrate Bit Line Contact And A Bit Line In DRAM, And Methods Of Forming DRAM Memory Cells 有权
    在DRAM中形成基板位线触点和位线之间的互连的方法以及形成DRAM存储单元的方法

    公开(公告)号：US20090197386A1

    公开(公告)日：2009-08-06

    申请号：US12419014

    申请日：2009-04-06

    申请人： Brett W. Busch ,  David K. Hwang ,  F. Daniel Gealy

    发明人： Brett W. Busch ,  David K. Hwang ,  F. Daniel Gealy

    IPC分类号： H01L21/8242 ,  H01L21/283 ,  H01L21/768

    CPC分类号： H01L21/76879 ,  B82Y10/00 ,  H01L21/28525 ,  H01L21/76885 ,  H01L21/76897 ,  H01L27/10811 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10888 ,  H01L28/91 ,  Y10S977/773

    摘要： The invention includes methods of electrically interconnecting different elevation conductive structures, methods of forming capacitors, methods of forming an interconnect between a substrate bit line contact and a bit line in DRAM, and methods of forming DRAM memory cells. In one implementation, a method of electrically interconnecting different elevation conductive structures includes forming a first conductive structure comprising a first electrically conductive surface at a first elevation of a substrate. A nanowhisker is grown from the first electrically conductive surface, and is provided to be electrically conductive. Electrically insulative material is provided about the nanowhisker. An electrically conductive material is deposited over the electrically insulative material in electrical contact with the nanowhisker at a second elevation which is elevationally outward of the first elevation, and the electrically conductive material is provided into a second conductive structure. Other aspects and implementations are contemplated.

    摘要翻译： 本发明包括电互连不同高程导电结构的方法，形成电容器的方法，在DRAM中形成衬底位线接触和位线之间的互连的方法，以及形成DRAM存储单元的方法。 在一个实施方式中，电连接不同高程导电结构的方法包括在衬底的第一高度处形成包括第一导电表面的第一导电结构。 纳米晶须从第一导电表面生长，并被提供为导电的。 提供关于纳米晶须的电绝缘材料。 导电材料沉积在电绝缘材料上，在第二高度处与纳米晶须电接触，第二高度位于第一高度的正上方，并且导电材料被提供到第二导电结构中。 考虑了其他方面和实现。

    Methods of forming DRAM memory cells
    4.
    发明授权
    Methods of forming DRAM memory cells 有权
    形成DRAM存储单元的方法

    公开(公告)号：US08030168B2

    公开(公告)日：2011-10-04

    申请号：US12419014

    申请日：2009-04-06

    申请人： Brett W. Busch ,  David K. Hwang ,  F. Daniel Gealy

    发明人： Brett W. Busch ,  David K. Hwang ,  F. Daniel Gealy

    IPC分类号： H01L21/8242

    CPC分类号： H01L21/76879 ,  B82Y10/00 ,  H01L21/28525 ,  H01L21/76885 ,  H01L21/76897 ,  H01L27/10811 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10888 ,  H01L28/91 ,  Y10S977/773

    摘要： The invention includes methods of electrically interconnecting different elevation conductive structures, methods of forming capacitors, methods of forming an interconnect between a substrate bit line contact and a bit line in DRAM, and methods of forming DRAM memory cells. In one implementation, a method of electrically interconnecting different elevation conductive structures includes forming a first conductive structure comprising a first electrically conductive surface at a first elevation of a substrate. A nanowhisker is grown from the first electrically conductive surface, and is provided to be electrically conductive. Electrically insulative material is provided about the nanowhisker. An electrically conductive material is deposited over the electrically insulative material in electrical contact with the nanowhisker at a second elevation which is elevationally outward of the first elevation, and the electrically conductive material is provided into a second conductive structure. Other aspects and implementations are contemplated.

    摘要翻译： 本发明包括电互连不同高程导电结构的方法，形成电容器的方法，在DRAM中形成衬底位线接触和位线之间的互连的方法，以及形成DRAM存储单元的方法。 在一个实施方式中，电连接不同高程导电结构的方法包括在衬底的第一高度处形成包括第一导电表面的第一导电结构。 纳米晶须从第一导电表面生长，并被提供为导电的。 提供关于纳米晶须的电绝缘材料。 导电材料沉积在电绝缘材料上，在第二高度处与纳米晶须电接触，第二高度位于第一高度的正上方，并且导电材料被提供到第二导电结构中。 考虑了其他方面和实现。

    Capacitors And Methods Of Forming Capacitors
    6.
    发明申请
    Capacitors And Methods Of Forming Capacitors 有权
    电容器和形成电容器的方法

    公开(公告)号：US20090244806A1

    公开(公告)日：2009-10-01

    申请号：US12480496

    申请日：2009-06-08

    申请人： Vishwanath Bhat ,  Noel Rocklein ,  F. Daniel Gealy

    发明人： Vishwanath Bhat ,  Noel Rocklein ,  F. Daniel Gealy

    IPC分类号： H01G4/008 ,  H01G9/00

    CPC分类号： H01L28/60 ,  Y10T29/417

    摘要： A method of forming a capacitor includes forming a conductive first capacitor electrode material comprising TiN over a substrate. TiN of the TiN-comprising material is oxidized effective to form conductive TiOxNy having resistivity no greater than 1 ohm·cm over the TiN-comprising material where x is greater than 0 and y is from 0 to 1.4. A capacitor dielectric is formed over the conductive TiOxNy. Conductive second capacitor electrode material is formed over the capacitor dielectric. Other aspects and implementations are contemplated, including capacitors independent of method of fabrication.

    摘要翻译： 形成电容器的方法包括在衬底上形成包含TiN的导电的第一电容器电极材料。 含TiN的材料的TiN被有效地氧化以形成电阻率不大于1欧姆·厘米的电导率TiO x N y，其中x大于0且y为0至1.4。 在导电TiO x N y上形成电容器电介质。 在电容器电介质上形成导电的第二电容器电极材料。 考虑了其他方面和实现方式，包括独立于制造方法的电容器。

    Method of forming a capacitor
    9.
    发明授权
    Method of forming a capacitor 失效
    形成电容器的方法

    公开(公告)号：US07041570B2

    公开(公告)日：2006-05-09

    申请号：US10299145

    申请日：2002-11-19

    申请人： F. Daniel Gealy ,  Thomas M. Graettinger

    发明人： F. Daniel Gealy ,  Thomas M. Graettinger

    IPC分类号： H01L21/20

    CPC分类号： H01L28/90 ,  H01G4/33 ,  H01L23/5223 ,  H01L28/55 ,  H01L28/65 ,  H01L28/84 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of forming a capacitor is disclosed. The method includes forming a first substrate layer, and forming a first electrode on the first substrate layer. The first electrode includes at least one non-smooth surface and is formed from a material selected from the group consisting of transition metals, conductive oxides, alloys thereof, and combinations thereof. The method also includes forming a dielectric on the first electrode and the first substrate layer, and forming a second electrode on the dielectric and the first substrate layer. The second electrode includes at least one non-smooth surface. The method further includes forming a second substrate layer on the second electrode.

    摘要翻译： 公开了形成电容器的方法。 该方法包括形成第一衬底层，并在第一衬底层上形成第一电极。 第一电极包括至少一个非光滑表面，并且由选自过渡金属，导电氧化物，其合金及其组合的材料形成。 该方法还包括在第一电极和第一衬底层上形成电介质，以及在电介质和第一衬底层上形成第二电极。 第二电极包括至少一个非光滑表面。 该方法还包括在第二电极上形成第二衬底层。

    Top electrode in a strongly oxidizing environment
    10.
    发明授权
    Top electrode in a strongly oxidizing environment 失效

    公开(公告)号：US07023043B2

    公开(公告)日：2006-04-04

    申请号：US10039215

    申请日：2002-01-03

    申请人： Cem Basceri ,  Howard E. Rhodes ,  Gurtej Sandhu ,  F. Daniel Gealy ,  Thomas M. Graettinger

    发明人： Cem Basceri ,  Howard E. Rhodes ,  Gurtej Sandhu ,  F. Daniel Gealy ,  Thomas M. Graettinger

    IPC分类号： H01L29/62

    CPC分类号： H01L28/65 ,  H01L21/31637 ,  H01L21/31691 ,  H01L23/5222 ,  H01L27/10852 ,  H01L28/56 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An improved charge storing device and methods for providing the same, the charge storing device comprising a conductor-insulator-conductor (CIC) sandwich. The CIC sandwich comprises a first conducting layer deposited on a semiconductor integrated circuit. The CIC sandwich further comprises a first insulating layer deposited over the first conducting layer in a flush manner. The first insulating layer comprises a structure having a plurality of oxygen cites and a plurality of oxygen atoms that partially fill the oxygen cites, wherein the unfilled oxygen cites define a concentration of oxygen vacancies. The CIC sandwich further comprises a second conducting layer deposited over the first insulating layer in a strongly oxidizing ambient so as to reduce the concentration of oxygen vacancies in the first insulating layer, so as to provide an oxygen-rich interface layer between the first insulating layer and the second conducting layer, and so as to trap a plurality of oxygen atoms within the second conducting layer. The oxygen-rich interface layer and second conducting layer act as oxygen vacancy sinks for absorbing migrating oxygen vacancies that originate from the first insulating layer to thereby reduce the concentration of oxygen vacancies in the first insulating layer and to thereby reduce the buildup of oxygen vacancies at the interface layer. Thus, the first insulating layer provides an increased dielectric constant and an increased resistance to current flowing therethrough so as to increase the capacitance of the CIC sandwich and so as to reduce leakage currents flowing through the CIC sandwich.