利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

18 条记录 (耗时 0.025 秒)

    Dishing resistance
    3.
    发明授权
    Dishing resistance 失效
    耐磨性

    公开(公告)号：US5928959A

    公开(公告)日：1999-07-27

    申请号：US940808

    申请日：1997-09-30

    申请人： Kai Huckels ,  Matthias Ilg

    发明人： Kai Huckels ,  Matthias Ilg

    IPC分类号： H01L21/3205 ,  H01L21/304 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/302

    CPC分类号： H01L21/31053 ,  H01L21/321 ,  H01L21/3212

    摘要： Fabrication of devices that produces a surface with reduced dishing caused by polishing. The reduced dishing is the result of forming a first layer that partially covers a complex surface topography and a second layer the covers the surface topography. The second layer being more resistant to polishing than the first so as to reduce dishing in the wide spaces of the complex topography.

    摘要翻译： 制造由抛光引起的凹陷减少的表面的装置。 减少的凹陷是形成部分覆盖复杂表面形貌的第一层和覆盖表面形貌的第二层的结果。 第二层比第一层更能抵抗抛光，以减少复杂形貌的宽空间中的凹陷。

    Method for forming a high surface area trench capacitor
    4.
    发明授权
    Method for forming a high surface area trench capacitor 失效
    高表面积沟槽电容器的形成方法

    公开(公告)号：US06319787B1

    公开(公告)日：2001-11-20

    申请号：US09107980

    申请日：1998-06-30

    申请人： Gerhard Enders ,  Matthias Ilg ,  Dietrich Widmann

    发明人： Gerhard Enders ,  Matthias Ilg ,  Dietrich Widmann

    IPC分类号： H01L2120

    CPC分类号： H01L27/10861 ,  H01L27/10829

    摘要： A trench capacitor having a substrate with a trench extending therein with a nested, e.g., concentric, conductive regions disposed within the trench. A dielectric material is disposed within the substrate. The dielectric material has portions thereof disposed between the concentric conductive regions to dielectrically electrically separate one of the conductive regions from another one of the conductive regions. The dielectrically separated conductive regions provide a pair of electrodes for the capacitor. Selected ones of the concentric conductive regions are electrically connected to provide one of the electrodes for the capacitor. The substrate has a conductive region therein and one of the concentric conductive regions providing one of the electrodes is electrically connected to the conductive region in the substrate. One of the concentric conductive regions is electrically connected to a conductive region in the substrate through a bottom portion of the trench.

    摘要翻译： 一种沟槽式电容器，其具有在其中延伸有沟槽的衬底，其具有设置在沟槽内的嵌套的，例如同心的导电区域。 电介质材料设置在衬底内。 电介质材料具有设置在同心导电区域之间的部分，以将导电区域中的一个与另一个导电区域电介质电分离。 介电分离的导电区域为电容器提供一对电极。 选择的同心导电区域被电连接以提供用于电容器的电极之一。 衬底在其中具有导电区域，并且提供电极之一的同心导电区域中的一个电连接到衬底中的导电区域。 一个同心导电区域通过沟槽的底部电连接到衬底中的导电区域。

    Uniform distribution of reactants in a device layer
    5.
    发明授权
    Uniform distribution of reactants in a device layer 失效
    反应物在器件层中的均匀分布

    公开(公告)号：US5807792A

    公开(公告)日：1998-09-15

    申请号：US768826

    申请日：1996-12-18

    申请人： Matthias Ilg ,  Markus Kirchhoff ,  Christoph Werner

    发明人： Matthias Ilg ,  Markus Kirchhoff ,  Christoph Werner

    IPC分类号： H01L21/683 ,  C23C16/44 ,  C23C16/455 ,  C30B25/14 ,  H01L21/205 ,  H01L21/31 ,  H01L21/316

    CPC分类号： H01L21/02271 ,  C23C16/44 ,  C23C16/455 ,  C30B25/14 ,  H01L21/02129 ,  H01L21/31625

    摘要： A method and apparatus for forming a multi-constituent device layer on a wafer surface are disclosed. The multi-constituent device layer is formed by flowing a first chemistry comprising a first constituent and a second chemistry comprising a second constituent via a segmented delivery system into a reaction chamber. The reaction chamber comprises a susceptor for supporting and rotating the wafers. The segmented delivery system comprises alternating first and second segments into which the first and second chemistries, respectively, are flowed. The first segments comprise an area that is greater than an area of the second segments by an amount sufficient to effectively reduce the diffusion path of the first constituent. Reducing the diffusion path of the first constituent results in a more uniform distribution of the first constituent within the device layer.

    摘要翻译： 公开了一种用于在晶片表面上形成多组分器件层的方法和装置。 通过将包含第一组分的第一化学物质和包含第二组分的第二化学物质通过分段递送系统流入反应室而形成多构成器件层。 反应室包括用于支撑和旋转晶片的基座。 分段递送系统包括交替的第一和第二段，第一和第二化学物质分别流入其中。 第一段包括大于第二段的面积的面积，其量足以有效地减小第一组分的扩散路径。 降低第一组分的扩散路径导致第一组分在器件层内的更均匀分布。

    Gapfill of semiconductor structure using doped silicate glasses
    8.
    发明授权
    Gapfill of semiconductor structure using doped silicate glasses 失效
    使用掺杂硅酸盐玻璃的半导体结构的填隙

    公开(公告)号：US6096654A

    公开(公告)日：2000-08-01

    申请号：US942273

    申请日：1997-09-30

    申请人： Markus M. Kirchhoff ,  Matthias Ilg

    发明人： Markus M. Kirchhoff ,  Matthias Ilg

    IPC分类号： H01L21/316 ,  H01L21/762 ,  H01L21/768 ,  H01L23/522 ,  H01L21/302

    CPC分类号： H01L21/76229 ,  H01L21/76837

    摘要： Improved gap fill of narrow spaces is achieved by using a doped silicate glass having a dopant concentration in a bottom portion thereof which is greater than an amount which causes surface crystal growth and in an upper portion thereof having a lower dopant concentration such that the overall dopant concentration of the doped silicate glass is below that which causes surface crystal growth.

    摘要翻译： 通过使用其底部中的掺杂剂浓度大于引起表面晶体生长的量的掺杂硅酸盐玻璃和其掺杂浓度较低的上部，使得全部掺杂剂 掺杂硅酸盐玻璃的浓度低于引起表面晶体生长的浓度。

    Advanced damascene planar stack capacitor fabrication method
    9.
    发明授权
    Advanced damascene planar stack capacitor fabrication method 失效
    高级大马士革平面堆叠电容器制造方法

    公开(公告)号：US6027968A

    公开(公告)日：2000-02-22

    申请号：US975193

    申请日：1997-11-20

    申请人： Son Van Nguyen ,  Matthias Ilg ,  Kevin J. Uram

    发明人： Son Van Nguyen ,  Matthias Ilg ,  Kevin J. Uram

    IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/1085 ,  H01L28/87

    摘要： Capacitor storage charge can be increased by increasing storage node area. A high aspect surface ratio stack capacitor is produced without increasing overall cell dimensions. The node is formed with layers of low doped and high doped concentration borophosphosilicate glass which is deposited by a single process step with precise nanometer dimensions, are selectively etched so that either doped or undoped layers will have a higher etch rate. This etching creates finger-like projections in the node, which provide for greater surface area using a very simplified process requiring fewer processing steps.

    摘要翻译： 可以通过增加存储节点面积来增加电容器存储费用。 在不增加整体电池尺寸的情况下制造高方位表面积比的电容器。 该节点由具有精确纳米尺寸的单个工艺步骤沉积的低掺杂和高掺杂浓度的硼磷硅酸盐玻璃层形成，被选择性地蚀刻，使得掺杂或未掺杂的层将具有更高的蚀刻速率。 该蚀刻在节点中产生指状突起，其使用需要更少处理步骤的非常简化的工艺来提供更大的表面积。

    Method of planarizing the semiconductor structure
    10.
    发明授权
    Method of planarizing the semiconductor structure 失效
    平面化半导体结构的方法

    公开(公告)号：US5963837A

    公开(公告)日：1999-10-05

    申请号：US846924

    申请日：1997-04-30

    申请人： Matthias Ilg ,  Dirk Tobben ,  Peter Weigand

    发明人： Matthias Ilg ,  Dirk Tobben ,  Peter Weigand

    IPC分类号： H01L21/3205 ,  H01L21/3105 ,  H01L21/316 ,  H01L21/768 ,  H01L29/78 ,  H01L21/02

    CPC分类号： H01L21/76819 ,  H01L21/31051 ,  H01L21/31053

    摘要： A method for planarizing a semiconductor structure having a first surface region with a high aspect ratio topography and a second surface region with a low aspect ratio topography. A flowable material is deposited over the first and second surface regions of the structure. A portion of the material fills gaps in the high aspect ratio topography to form a substantially planar surface over the high aspect ratio topography. A doped layer, for example phosphorus doped glass, is formed over the flowable oxide material. The doped layer is disposed over the high aspect ratio and over the low aspect ratio regions. Upper surface portions over the low aspect ratio region are higher than an upper surface of the flowable material. The upper portion of the doped layer is removed over both the first and second surface portions to form a layer with a substantially planar surface above both the high aspect ratio region and the low aspect ratio region. The method is used for filling gaps, such as gaps between adjacent gate electrodes formed in a gate electrode surface region of a semiconductor structure.

    摘要翻译： 一种用于平面化具有高纵横比拓扑的第一表面区域和具有低纵横比拓扑的第二表面区域的半导体结构的方法。 可流动材料沉积在结构的第一和第二表面区域上。 材料的一部分填充高纵横比拓扑中的间隙，以在高纵横比拓扑上形成基本平坦的表面。 在可流动氧化物材料上形成掺杂层，例如磷掺杂玻璃。 掺杂层设置在高纵横比和低纵横比区域之上。 低纵横比区域上的上表面部分高于可流动材料的上表面。 在第一和第二表面部分上去除掺杂层的上部，以形成在高纵横比区域和低纵横比区域之上具有基本平坦表面的层。 该方法用于填充间隙，例如形成在半导体结构的栅电极表面区域中的相邻栅电极之间的间隙。