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公开(公告)号:US11817490B2
公开(公告)日:2023-11-14
申请号:US17403215
申请日:2021-08-16
发明人: Louis Hutin , Julien Borrel , Raluca Tiron
IPC分类号: H01L21/265 , H01L21/308 , H01L21/266 , H01L29/66 , G06N10/00 , B82Y40/00
CPC分类号: H01L29/66439 , G06N10/00 , H01L21/26506 , H01L21/308 , B82Y40/00
摘要: A method for making a quantum device including:
forming, over a semiconductor layer, a graphoepitaxy guide forming a cavity with a lateral dimension that is a multiple of a period of self-assembly of a di-block copolymer into lamellas;
first deposition of the copolymer in the cavity;
first self-assembly of the copolymer, forming a first alternating arrangement of first lamellas and of second lamellas;
removal of the first lamellas;
implantation of dopants in portions of the semiconductor layer previously covered with the first lamellas;
removal of the second lamellas;
second deposition of the copolymer in the cavity, over a gate material;
second self-assembly of the copolymer, forming a second alternating arrangement of first and second lamellas;
removal of the second lamellas;
etching of portions of the gate material previously covered with the second lamellas.-
公开(公告)号:US20160260819A1
公开(公告)日:2016-09-08
申请号:US15058615
申请日:2016-03-02
IPC分类号: H01L29/66 , H01L21/768 , H01L29/51 , H01L23/535 , H01L29/772 , H01L29/423
CPC分类号: H01L29/66553 , H01L21/76897 , H01L23/535 , H01L29/0895 , H01L29/42364 , H01L29/512 , H01L29/772
摘要: A field-effect transistor, including a source, drain and channel formed in a semiconductor layer a gate stack placed above the channel, including a metal electrode, a first layer of electrical insulator placed between the metal electrode and the channel, and a second layer of electrical insulator covering the metal electrode; a metal contact placed plumb with the source or drain and at least partially plumb with said gate stack; and a third layer of electrical insulator placed between said metal contact and said source or said drain.
摘要翻译: 一种场效应晶体管,包括在半导体层中形成的源极,漏极和沟道,位于沟道上方的栅极堆叠,包括金属电极,放置在金属电极和沟道之间的第一绝缘体层和第二层 覆盖金属电极的电绝缘体; 金属接触件放置铅与源或漏极并且至少部分地与所述栅极叠层相垂直; 以及放置在所述金属触点和所述源极或所述漏极之间的第三层电绝缘体。
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公开(公告)号:US11362051B2
公开(公告)日:2022-06-14
申请号:US17199610
申请日:2021-03-12
发明人: Jean-Pierre Colinge , Louis Hutin , Maxime Moulin , Thibaud Fache
IPC分类号: H01L23/66 , H01L21/762 , H01L27/12 , H01L23/14
摘要: Making a semiconductor-on-insulator substrate provided with an eddy current blocking structure (20) formed in a segment (22) doped according to doping of a first type, of doped regions (23) periodically distributed on one or more parallel rows and according to a pattern (M2) and an improved arrangement.
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公开(公告)号:US11329145B2
公开(公告)日:2022-05-10
申请号:US16159923
申请日:2018-10-15
发明人: Louis Hutin , Xavier Jehl , Maud Vinet
IPC分类号: H01L29/66 , H01L29/06 , H01L29/423 , B82Y10/00 , H01L29/76 , H01L21/265 , H01L21/266 , H01L29/36 , H01L29/40 , H01L29/417 , H01L29/786
摘要: A quantum device with spin qubits, comprising: a semiconductor portion arranged on a buried dielectric layer of a semiconductor-on-insulator substrate also including a semiconductor support layer, wherein first distinct parts each form a confinement region of one of the qubits and are spaced apart from one another by a second part forming a coupling region between the confinement regions of the qubits; front gates each at least partially covering one of the first parts of the semiconductor portion; and wherein the support layer comprises a doped region a part of which is arranged in line with the second part of the semiconductor portion and is self-aligned with respect to the front gates, and forms a back gate controlling the coupling between the confinement regions of the qubits.
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公开(公告)号:US09911841B2
公开(公告)日:2018-03-06
申请号:US15066590
申请日:2016-03-10
发明人: Sylvain Barraud , Ivan Duchemin , Louis Hutin , Yann-Michel Niquet , Maud Vinet
CPC分类号: H01L29/7613 , B82Y10/00 , H01L29/0665 , H01L29/0669 , H01L29/1033 , H01L29/66439 , H01L29/66469 , H01L29/66545 , H01L29/78618 , H01L29/78696
摘要: Single-electron transistor comprising at least: first semiconductor portions forming source and drain regions, a second semiconductor portion forming at least one quantum island, third semiconductor portions forming tunnel junctions between the second semiconductor portion and the first semiconductor portions, a gate and a gate dielectric located on at least the second semiconductor portion, in which a thickness of each of the first semiconductor portions is greater than the thickness of the second semiconductor portion, and in which a thickness of the second semiconductor portion is greater than the thickness of each of the third semiconductor portions.
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公开(公告)号:US10903349B2
公开(公告)日:2021-01-26
申请号:US16413646
申请日:2019-05-16
发明人: Louis Hutin , Sylvain Barraud , Benoit Bertrand , Maud Vinet
IPC分类号: H01L29/06 , H01L29/775 , H01L29/423 , H01L29/66
摘要: An electronic component with multiple quantum islands is provided, including a substrate on which rests a nanowire made of semiconductor material not intentionally doped; two main control gates resting on the nanowire so as to form respective qubits in the nanowire, the two main control gates being separated by a groove, and bottom and lateral faces of the groove are covered by a dielectric layer; an element made of conductive material formed on the dielectric layer in the groove; a carrier reservoir that is offset with respect to the nanowire, the element made of the conductive material being separated from the carrier reservoir by another dielectric layer such that the element made of the conductive material is coupled to the carrier reservoir by field effect. A method of fabricating an electronic component with multiple quantum islands is also provided.
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公开(公告)号:US20180331108A1
公开(公告)日:2018-11-15
申请号:US15967778
申请日:2018-05-01
申请人: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES , CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE
IPC分类号: H01L27/105 , H01L29/66 , H01L23/522 , G06N99/00
CPC分类号: G06N99/002
摘要: A quantum device with spin qubits, comprising: a first semiconducting layer comprising a first matrix of data qubits and measurement qubits connected to each other through tunnel barriers; means of addressing qubits configured for controlling conduction of each tunnel barrier by the field effect and comprising: first and second conducting portions arranged in first and second superposed metallisation levels respectively; first and second conducting vias each comprising a first end connected to one of the first and second conducting portions respectively, and a second end located facing one of the tunnel barriers; a first dielectric layer interposed between the tunnel barriers and the second ends of the first and second conducting vias.
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公开(公告)号:US09911827B2
公开(公告)日:2018-03-06
申请号:US15372930
申请日:2016-12-08
申请人: Commissariat a l'energie atomique et aux energies alternatives , STMicroelectronics SA , STMicroelectronics (Crolles 2) SAS
发明人: Louis Hutin , Julien Borrel , Yves Morand , Fabrice Nemouchi
CPC分类号: H01L29/66643 , H01L29/0895 , H01L29/66636 , H01L29/7839
摘要: A process for manufacturing a Schottky barrier field-effect transistor is provided. The process includes: providing a structure including a control gate and a semiconductive layer positioned under the gate and having protrusions that protrude laterally with respect to the gate; anisotropically etching at least one of the protrusions by using the control gate as a mask, so as to form a recess in this protrusion, this recess defining a lateral face of the semiconductive layer; depositing a layer of insulator on the lateral face of the semiconductive layer; and depositing a metal in the recess on the layer of insulator so as to form a contact of metal/insulator/semiconductor type between the deposit of metal and the lateral face of the semiconductive layer.
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公开(公告)号:US20170271470A1
公开(公告)日:2017-09-21
申请号:US15464763
申请日:2017-03-21
申请人: Commissariat a l'energie atomique et aux energies alternatives , STMicroelectronics SA , STMicroelectronics (Crolles 2) SAS
IPC分类号: H01L29/49 , H01L21/768 , H01L29/06 , H01L29/66 , H01L29/51 , H01L23/535
CPC分类号: H01L29/4983 , H01L21/76895 , H01L23/535 , H01L29/0649 , H01L29/517 , H01L29/6653 , H01L29/66545 , H01L29/66606 , H01L29/66628
摘要: A method of fabrication, including the steps for supplying a substrate including a layer of semiconductor material covered by a sacrificial gate including a sacrificial gate insulator including a middle part, and edges covered by sacrificial spacers and having a thickness tox; removal of the sacrificial gate insulator and the sacrificial gate material; formation of a conformal deposition of thickness thk of dielectric material inside of the groove formed in order to form a gate insulator, with tox>thk≧tox/2; formation of a gate electrode within the groove; removal of the sacrificial spacers so as to open up edges of the gate insulator layer; formation of spacers on the edges of the gate insulator layer on either side of the gate electrode, these spacers having a dielectric constant at the most equal to 3.5.
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公开(公告)号:US11941485B2
公开(公告)日:2024-03-26
申请号:US17456388
申请日:2021-11-24
发明人: Nicolas Posseme , Louis Hutin , Cyrille Le Royer , François Lefloch , Fabrice Nemouchi , Maud Vinet
CPC分类号: G06N10/00 , H01L29/66977 , H10N60/01 , H10N60/128
摘要: A method for producing a quantum device comprising providing a substrate having a front face and carrying at least one transistor pattern on the front face thereof, said transistor pattern comprising, in a stack a gate dielectric on the front face of the substrate, and a gate on the gate dielectric, said gate having a top and sidewalls. The method further includes forming a protective layer at the front face of the substrate, said protective layer being configured to prevent diffusion of at least one metal species in the substrate, forming a metal layer that has, as a main component, at least one metal species, at least on the sidewalls of the gate, said at least one metal species comprising at least one superconducting element, and forming a superconducting region in the gate by lateral diffusion of the at least one superconducting element from the sidewalls of said gate.
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