利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

26 条记录 (耗时 0.017 秒)

    Dual damascene cleaning method
    4.
    发明授权
    Dual damascene cleaning method 有权
    双镶嵌清洗方法

    公开(公告)号：US07329956B1

    公开(公告)日：2008-02-12

    申请号：US11519625

    申请日：2006-09-12

    申请人： Chen-Hua Yu ,  Ching-Ya Wang

    发明人： Chen-Hua Yu ,  Ching-Ya Wang

    IPC分类号： H01L23/58 ,  H01L23/52

    CPC分类号： H01L23/53295 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76865 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor structure having a pore sealed portion of a dielectric layer is provided. Exposed pores of the dielectric material are sealed using an anisotropic plasma so that pores along the bottom of the opening are sealed, and pores along sidewalls of the opening remain relatively untreated by the plasma. Thereafter, one or more barrier layers may be formed and the opening may be filled with a conductive material. The barrier layers formed over the sealing layer exhibits a more continuous barrier layer. The pores may be partially or completely sealed by plasma bombardment or ion implantation using a gas selected from one of O2, an O2/N2 mixture, H2O, or combinations thereof.

    摘要翻译： 提供具有介电层的密封部分的半导体结构。 使用各向异性等离子体密封电介质材料的露出孔，使得沿着开口底部的孔被密封，并且沿着开口侧壁的孔保持相对未被等离子体处理。 此后，可以形成一个或多个阻挡层，并且可以用导电材料填充该开口。 形成在密封层之上的阻挡层表现出更连续的阻挡层。 通过等离子体轰击或离子注入可以使用选自O 2 O 2，N 2 / N 2 N 2中的一种的气体部分或完全地密封孔。 >混合物，H 2 O，或其组合。

    Method to create damage-free porous Low-k dielectric films and structures resulting therefrom
    5.
    发明申请
    Method to create damage-free porous Low-k dielectric films and structures resulting therefrom 有权
    制造无损多孔Low-k电介质膜和由此产生的结构的方法

    公开(公告)号：US20070111535A1

    公开(公告)日：2007-05-17

    申请号：US11273701

    申请日：2005-11-14

    申请人： Chen-Hua Yu ,  Ching-Ya Wang

    发明人： Chen-Hua Yu ,  Ching-Ya Wang

    IPC分类号： H01L21/31

    CPC分类号： H01L21/3105 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02271 ,  H01L21/02282 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/31695 ,  H01L21/76802 ,  H01L21/76826 ,  Y10S438/96

    摘要： Low dielectric constant dielectric films having a high degree of porosity suffer from poor mechanical strength and can be damaged during processing steps. Damage can be substantially eliminated or minimized by stuffing the pores of the dielectric film with a material that substantially fills the pores. The stuffing material should have low surface tension and viscosity to provide good wetting. Alternatively, the stuffing material can be dissolved in a wetting carrier fluid, such as supercritical carbon dioxide and the like.

    摘要翻译： 具有高孔隙率的低介电常数电介质膜具有差的机械强度并且在加工步骤期间可能被损坏。 通过用基本上填充孔的材料填充电介质膜的孔隙可以基本消除或最小化损伤。 填料应具有较低的表面张力和粘度，以提供良好的润湿性。 或者，填充材料可以溶解在润​​湿载体流体中，例如超临界二氧化碳等。

    Contact barrier structure and manufacturing methods
    6.
    发明授权
    Contact barrier structure and manufacturing methods 有权
    接触屏障结构及制造方法

    公开(公告)号：US07709903B2

    公开(公告)日：2010-05-04

    申请号：US11807127

    申请日：2007-05-25

    申请人： Ching-Ya Wang ,  Chung-Hu Ke ,  Wen-Chin Lee

    发明人： Ching-Ya Wang ,  Chung-Hu Ke ,  Wen-Chin Lee

    IPC分类号： H01L29/94

    CPC分类号： H01L29/7848 ,  H01L21/28518 ,  H01L21/76844 ,  H01L21/7685 ,  H01L29/665 ,  H01L29/66515 ,  H01L29/6659 ,  H01L29/7833

    摘要： A semiconductor structure includes a semiconductor substrate; a gate dielectric over the semiconductor substrate; a gate electrode over the gate dielectric; a source/drain region adjacent the gate dielectric; a silicide region on the source/drain region; a metal layer on top of, and physical contacting, the silicide region; an inter-layer dielectric (ILD) over the metal layer; and a contact opening in the ILD. The metal layer is exposed through the contact opening. The metal layer further extends under the ILD. The semiconductor structure further includes a contact in the contact opening.

    摘要翻译： 半导体结构包括半导体衬底; 半导体衬底上的栅极电介质; 位于栅极电介质上的栅电极; 与栅极电介质相邻的源极/漏极区域; 源/漏区上的硅化物区; 硅化物区域的顶部和物理接触处的金属层; 金属层上的层间电介质（ILD）; 和ILD的接触开口。 金属层通过接触开口露出。 金属层进一步在ILD下延伸。 半导体结构还包括接触开口中的接触。

    Method for improving low-K dielectrics by supercritical fluid treatments
    7.
    发明授权
    Method for improving low-K dielectrics by supercritical fluid treatments 有权
    通过超临界流体处理改善低K电介质的方法

    公开(公告)号：US07387973B2

    公开(公告)日：2008-06-17

    申请号：US10956640

    申请日：2004-09-30

    申请人： Ching-Ya Wang ,  Joshua Tseng ,  Henry Lo

    发明人： Ching-Ya Wang ,  Joshua Tseng ,  Henry Lo

    IPC分类号： H01L21/31 ,  H01L21/469

    CPC分类号： H01L21/76826 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76877

    摘要： A method for treating an inter-metal dielectric (IMD) layer to improve a mechanical strength and/or repair plasma etching damage including providing a low-K silicon oxide containing dielectric insulating layer; and carrying out a super critical fluid treatment of the low-K dielectric insulating layer including supercritical CO2 and a solvent including a silicon bond forming substituent having a bonding energy greater than a Si—H to replace at least a portion of the Si—H bonds with the silicon bond forming substituent.

    摘要翻译： 一种用于处理金属间电介质（IMD）层以改善机械强度和/或修复等离子体蚀刻损伤的方法，包括提供含有低K氧化硅的介电绝缘层; 并对包括超临界CO 2的低K电介质绝缘层进行超临界流体处理，并且包括具有大于Si-H的键合能力的形成硅键的取代基的溶剂至少替代 一部分Si-H与形成硅键的取代基键合。

    Tunnel Field-Effect Transistors with Superlattice Channels
    8.
    发明申请
    Tunnel Field-Effect Transistors with Superlattice Channels 有权
    具超晶格通道的隧道场效应晶体管

    公开(公告)号：US20110027959A1

    公开(公告)日：2011-02-03

    申请号：US12898421

    申请日：2010-10-05

    申请人： Krishna Kumar Bhuwalka ,  Ching-Ya Wang ,  Ken-Ichi Goto ,  Wen-Chin Lee ,  Carlos H. Diaz

    发明人： Krishna Kumar Bhuwalka ,  Ching-Ya Wang ,  Ken-Ichi Goto ,  Wen-Chin Lee ,  Carlos H. Diaz

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7391 ,  H01L21/26586

    摘要： A semiconductor device includes a channel region; a gate dielectric over the channel region; a gate electrode over the gate dielectric; and a first source/drain region adjacent the gate dielectric. The first source/drain region is of a first conductivity type. At least one of the channel region and the first source/drain region includes a superlattice structure. The semiconductor device further includes a second source/drain region on an opposite side of the channel region than the first source/drain region. The second source/drain region is of a second conductivity type opposite the first conductivity type. At most, one of the first source/drain region and the second source/drain region comprises an additional superlattice structure.

    摘要翻译： 半导体器件包括沟道区; 沟道区上的栅极电介质; 位于栅极电介质上的栅电极; 以及与栅极电介质相邻的第一源极/漏极区域。 第一源极/漏极区域是第一导电类型。 沟道区域和第一源极/漏极区域中的至少一个包括超晶格结构。 所述半导体器件还包括与所述第一源极/漏极区域相比在所述沟道区域的相对侧上的第二源极/漏极区域。 第二源极/漏极区域是与第一导电类型相反的第二导电类型。 最多，第一源极/漏极区域和第二源极/漏极区域中的一个包括附加的超晶格结构。