公开(公告)号：US20050087873A1

公开(公告)日：2005-04-28

申请号：US10948046

申请日：2004-09-22

申请人： Chih-I Wu ,  Jihperng Leu

发明人： Chih-I Wu ,  Jihperng Leu

IPC分类号： C23C16/34 ,  H01L21/285 ,  H01L21/768 ,  H01L21/4763 ,  H01L21/44 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76849 ,  C23C16/34 ,  H01L21/28562

摘要： Method and structure for passivating conductive material are disclosed. Atomic layer deposition of a thin passivation layer such as titanium nitride upon a conductive layer comprising a material such as copper, in the presence of a dielectric material not conductive to surface reaction with gaseous precursors used in the deposition schema, facilitates highly selective and accurate passivation which may improve electromigration performance, minimize leakage current to other conductive layers, and streamline process steps.

摘要翻译： 公开了钝化导电材料的方法和结构。 在存在不能与沉积模式中使用的气体前体进行表面反应的电介质材料存在下，包括诸如铜的导电层的薄钝化层如氮化钛的原子层沉积促进了高选择性和准确的钝化 这可以改善电迁移性能，使对其它导电层的泄漏电流最小化，并简化工艺步骤。

公开(公告)号：US06743712B2

公开(公告)日：2004-06-01

申请号：US10195032

申请日：2002-07-12

申请人： Hyun-Mog Park ,  Jihperng Leu ,  Chih-I Wu

发明人： Hyun-Mog Park ,  Jihperng Leu ,  Chih-I Wu

IPC分类号： H01L214763

CPC分类号： H01L21/76816 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76804 ,  H01L21/76807 ,  Y10S438/947

摘要： A method for making a semiconductor device is described. That method includes forming a sacrificial layer on a substrate, then forming a layer of photoresist on the sacrificial layer. After the photoresist layer is patterned, to form a patterned photoresist layer that has a first opening, part of the sacrificial layer is removed to generate an etched sacrificial layer that has a second opening that is substantially smaller than the first opening.

摘要翻译： 描述制造半导体器件的方法。 该方法包括在衬底上形成牺牲层，然后在牺牲层上形成光致抗蚀剂层。 在光致抗蚀剂层被图案化之后，为了形成具有第一开口的图案化光致抗蚀剂层，去除了牺牲层的一部分以产生蚀刻的牺牲层，其具有基本上小于第一开口的第二开口。

公开(公告)号：US06605549B2

公开(公告)日：2003-08-12

申请号：US09968212

申请日：2001-09-29

申请人： Jihperng Leu ,  Chih-I Wu ,  Ying Zhou ,  Grant M. Kloster

发明人： Jihperng Leu ,  Chih-I Wu ,  Ying Zhou ,  Grant M. Kloster

IPC分类号： H01L2131

CPC分类号： H01L21/32051 ,  C23C16/02 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76843 ,  H01L21/76873 ,  H01L21/76874

摘要： A method to improve nucleation and/or adhesion of a CVD or ALD-deposited film/layer onto a low-dielectric constant (low-k) dielectric layer, such as a polymeric dielectric or a carbon-doped oxide. In an embodiment, the method includes providing a substrate into a deposition chamber. A dielectric layer having a reactive component is formed over the substrate. The formed dielectric layer having the reactive component is then processed to produce polar groups or polar sites at least on a surface of the formed dielectric layer. The present invention forms a low-k organic polymer dielectric layer or an organic-doped oxide dielectric layer having improved nucleation and/or adhesion properties for a subsequently deposited layer such as a barrier material layer.

摘要翻译： 改善CVD或ALD沉积膜/层在低介电常数（低k）电介质层（例如聚合物电介质或碳掺杂氧化物）上的成核和/或粘附的方法。 在一个实施例中，该方法包括将衬底提供到沉积室中。 在基板上形成具有反应成分的电介质层。 然后将形成的具有反应性组分的介电层至少在形成的介电层的表面上进行处理以产生极性基团或极性位点。 本发明形成低k有机聚合物介电层或有机掺杂的氧化物介电层，其具有改进的成核和/或粘合性能，用于随后沉积的层例如阻挡材料层。

公开(公告)号：US20050224980A1

公开(公告)日：2005-10-13

申请号：US10816470

申请日：2004-03-31

申请人： Jihperng Leu ,  Chih-I Wu ,  Mark Liu ,  Kevin Fischer ,  Chia-Hong Jan ,  David Gracias

发明人： Jihperng Leu ,  Chih-I Wu ,  Mark Liu ,  Kevin Fischer ,  Chia-Hong Jan ,  David Gracias

IPC分类号： H01L21/288 ,  H01L21/44 ,  H01L21/768

CPC分类号： H01L21/2885 ,  H01L21/76888

摘要： A die is provided with an interconnect, and the grain structure of the interconnect is adapted to reduce electron scattering.

摘要翻译： 模具设置有互连，并且互连的晶粒结构适于减少电子散射。

公开(公告)号：US07727892B2

公开(公告)日：2010-06-01

申请号：US10255930

申请日：2002-09-25

申请人： Xiaorong Morrow ,  Jihperng Leu ,  Markus Kuhn ,  Jose A. Maiz

发明人： Xiaorong Morrow ,  Jihperng Leu ,  Markus Kuhn ,  Jose A. Maiz

IPC分类号： H01L21/311

CPC分类号： H01L21/76849 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76855 ,  H01L21/76888 ,  H01L21/76897 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： Described is a method and apparatus for forming interconnects with a metal-metal oxide electromigration barrier and etch-stop. In one embodiment of the invention, the method includes depositing a metal layer on the top of a planarized interconnect layer, the interconnect layer having an interlayer dielectric (ILD) with a top that is planar with the top of an electrically conductive interconnect. In one embodiment of the invention, the method includes reacting the metal layer with the ILD to form a metal oxide layer on the top of the ILD. At the same time, the metal layer will not be significantly oxidized by the electrically conductive interconnect, thus forming a metal barrier on the electrically conductive interconnect to improve electromigration performance. The metal barrier and metal oxide layer together comprise a protective layer. A second ILD may be subsequently formed on the protective layer, and the protective layer may act an etch-stop during a subsequent etch of the second ILD.

摘要翻译： 描述了用于与金属 - 金属氧化物电迁移屏障和蚀刻停止形成互连的方法和装置。 在本发明的一个实施例中，该方法包括在平坦化的互连层的顶部上沉积金属层，所述互连层具有层间电介质（ILD），其顶部与导电互连的顶部是平面的。 在本发明的一个实施方案中，该方法包括使金属层与ILD反应以在ILD的顶部形成金属氧化物层。 同时，金属层不会被导电互连显着地氧化，从而在导电互连上形成金属阻挡层以改善电迁移性能。 金属屏障和金属氧化物层一起包括保护层。 随后可以在保护层上形成第二ILD，并且保护层可以在随后的第二ILD蚀刻期间进行蚀刻停止。

公开(公告)号：US07214594B2

公开(公告)日：2007-05-08

申请号：US10105431

申请日：2002-03-26

申请人： Lawrence D. Wong ,  Jihperng Leu ,  Grant Kloster ,  Andrew Ott ,  Patrick Morrow

发明人： Lawrence D. Wong ,  Jihperng Leu ,  Grant Kloster ,  Andrew Ott ,  Patrick Morrow

IPC分类号： H01L21/00 ,  H01L21/82 ,  H01L21/76 ,  H01L21/265 ,  H01L21/44 ,  H01L29/80

CPC分类号： H01L21/76852 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76885 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and apparatus are provided an interconnect cladding layer. In one embodiment, a first sacrificial layer is deposited over a substrate and patterned. In the vias created during the patterning operation, a conductive material is placed to create conductive interconnects. After planarizing the conductive material, the sacrificial layer is removed leaving the interconnect exposed. A cladding layer is then deposited over the conductive material.

摘要翻译： 一种方法和装置设置有互连包层。 在一个实施例中，第一牺牲层沉积在衬底上并被图案化。 在图案化操作期间形成的通孔中，放置导电材料以产生导电互连。 在平坦化导电材料之后，去除牺牲层，使互连体暴露。 然后在导电材料上沉积包覆层。

公开(公告)号：US06998216B2

公开(公告)日：2006-02-14

申请号：US10253723

申请日：2002-09-24

申请人： Jun He ,  Jihperng Leu

发明人： Jun He ,  Jihperng Leu

IPC分类号： G03C5/00 ,  H01L21/31

CPC分类号： H01L21/76831 ,  H01L21/76801 ,  H01L21/76808 ,  H01L21/7682 ,  H01L21/76825 ,  H01L23/5222 ,  H01L23/5226 ,  H01L2924/0002 ,  Y10S430/143 ,  H01L2924/00

摘要： In an embodiment, a trench is formed above a via from a photo resist (PR) trench pattern in a dielectric layer. The trench is defined by two sidewall portions and base portions. The base portions of the sidewalls are locally treated by a post treatment using the PR trench pattern as mask to enhance mechanical strength of portions of the dielectric layer underneath the base portions. Seed and barrier layers are deposited on the trench and the via. The trench and via are filled with a metal layer. In another embodiment, a trench is formed from a PR trench pattern in a dielectric layer. A pillar PR is deposited and etched to define a pillar opening having a pillar surface. The pillar opening is locally treated on the pillar surface by a post treatment to enhance mechanical strength of portion of the dielectric layer underneath the pillar surface.

摘要翻译： 在一个实施例中，在电介质层中的光致抗蚀剂（PR）沟槽图案的通孔上方形成沟槽。 沟槽由两个侧壁部分和基部限定。 通过使用PR沟槽图案作为掩模的后处理对侧壁的基部进行局部处理，以增强在基部下方的介电层的部分的机械强度。 种子和阻挡层沉积在沟槽和通孔上。 沟槽和通孔填充有金属层。 在另一个实施例中，沟槽由电介质层中的PR沟槽图案形成。 沉积并蚀刻柱PR以限定具有柱表面的柱开口。 通过后处理在柱面上局部处理立柱开口，以提高柱表面下方的电介质层的部分的机械强度。

公开(公告)号：US20050236714A1

公开(公告)日：2005-10-27

申请号：US11170322

申请日：2005-06-28

申请人： Jihperng Leu ,  Grant Kloster ,  David Gracias ,  Lee Rockford ,  Peter Moon ,  Chris Barns

发明人： Jihperng Leu ,  Grant Kloster ,  David Gracias ,  Lee Rockford ,  Peter Moon ,  Chris Barns

IPC分类号： H01L21/312 ,  H01L21/316 ,  H01L21/768 ,  H01L23/48

CPC分类号： H01L21/76835 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/312 ,  H01L21/3124 ,  H01L21/31695 ,  H01L21/76807 ,  H01L21/7682

摘要： An inter-layer dielectric structure and method of making such structure are disclosed. A composite dielectric layer, initially comprising a porous matrix and a porogen, is formed. Subsequent to other processing treatments, the porogen is decomposed and removed from at least a portion of the porous matrix, leaving voids defined by the porous matrix in areas previously occupied by the porogen. The resultant structure has a desirably low k value as a result of the porosity and materials comprising the porous matrix and porogen. The composite dielectric layer may be used in concert with other dielectric layers of varying porosity, dimensions, and material properties to provide varied mechanical and electrical performance profiles.

摘要翻译： 公开了一种层间电介质结构及其制造方法。 形成初始包含多孔基质和致孔剂的复合介电层。 在其它处理处理之后，致孔剂从多孔基体的至少一部分分解和除去，留下由多孔基质定义的空隙，其中先前由致孔剂占据的区域。 所得结构由于孔隙率和包含多孔基质和致孔剂的材料而具有期望的低k值。 复合介电层可以与具有不同孔隙率，尺寸和材料性质的其它电介质层一起使用，以提供不同的机械和电气性能轮廓。

公开(公告)号：US08963421B2

公开(公告)日：2015-02-24

申请号：US13616442

申请日：2012-09-14

申请人： Jihperng Leu ,  Shu-Hao Syu ,  Hung-En Tu ,  Chih Wang

发明人： Jihperng Leu ,  Shu-Hao Syu ,  Hung-En Tu ,  Chih Wang

IPC分类号： H05B33/12

CPC分类号： H01L51/5256

摘要： An electroluminescent device includes: a substrate; an electroluminescent layered structure disposed over the substrate and including first and second electrode layers and an electroluminescent material layer disposed between the first and second electrode layers; and a moisture barrier layer in contact with the electroluminescent layered structure for preventing moisture from diffusing into the electroluminescent layered structure. The moisture barrier layer includes at least two inorganic films of a silicon-nitrogen-containing compound and at least one polymer film interposed between the inorganic films.

摘要翻译： 电致发光器件包括：衬底; 设置在所述基板上并且包括第一和第二电极层的电致发光层状结构和设置在所述第一和第二电极层之间的电致发光材料层; 以及与电致发光层状结构接触的防潮层，用于防止水分扩散到电致发光层状结构中。 防潮层包括至少两种含硅的化合物的无机膜和介于无机膜之间的至少一种聚合物膜。

公开(公告)号：US07239019B2

公开(公告)日：2007-07-03

申请号：US11170322

申请日：2005-06-28

申请人： Jihperng Leu ,  Grant M. Kloster ,  David H. Gracias ,  Lee D. Rockford ,  Peter K. Moon ,  Chris E. Barns

发明人： Jihperng Leu ,  Grant M. Kloster ,  David H. Gracias ,  Lee D. Rockford ,  Peter K. Moon ,  Chris E. Barns

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76835 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/312 ,  H01L21/3124 ,  H01L21/31695 ,  H01L21/76807 ,  H01L21/7682

摘要： An inter-layer dielectric structure and method of making such structure are disclosed. A composite dielectric layer, initially comprising a porous matrix and a porogen, is formed. Subsequent to other processing treatments, the porogen is decomposed and removed from at least a portion of the porous matrix, leaving voids defined by the porous matrix in areas previously occupied by the porogen. The resultant structure has a desirably low k value as a result of the porosity and materials comprising the porous matrix and porogen. The composite dielectric layer may be used in concert with other dielectric layers of varying porosity, dimensions, and material properties to provide varied mechanical and electrical performance profiles.

摘要翻译： 公开了一种层间电介质结构及其制造方法。 形成初始包含多孔基质和致孔剂的复合介电层。 在其它处理处理之后，致孔剂从多孔基体的至少一部分分解和除去，留下由多孔基质定义的空隙，其中先前由致孔剂占据的区域。 所得结构由于孔隙率和包含多孔基质和致孔剂的材料而具有期望的低k值。 复合介电层可以与具有不同孔隙率，尺寸和材料性质的其它电介质层一起使用，以提供不同的机械和电气性能轮廓。