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    SEMICONDUCTOR PACKAGE AND LEAD FRAME THEREOF
    3.
    发明申请
    SEMICONDUCTOR PACKAGE AND LEAD FRAME THEREOF 有权
    半导体封装和引线框架

    公开(公告)号：US20130334671A1

    公开(公告)日：2013-12-19

    申请号：US13613309

    申请日：2012-09-13

    申请人： Chih-Ming Kuo ,  Shih-Chieh Chang ,  Chih-Hsien Ni ,  Chin-Tang Hsieh ,  Chia-Jung Tu ,  Lung-Hua Ho

    发明人： Chih-Ming Kuo ,  Shih-Chieh Chang ,  Chih-Hsien Ni ,  Chin-Tang Hsieh ,  Chia-Jung Tu ,  Lung-Hua Ho

    IPC分类号： H01L23/495

    CPC分类号： H01L24/16 ,  H01L21/4828 ,  H01L23/3107 ,  H01L23/49548 ,  H01L23/49572 ,  H01L23/49582 ,  H01L2224/16245 ,  H01L2924/181 ,  H01L2924/00

    摘要： A semiconductor package includes a lead frame, at least one chip and a molding compound. The lead frame comprises a plurality of leads, each lead comprises a first end portion and at least one coupling protrusion, wherein the first end portion comprises a first upper surface, the coupling protrusion comprises a ring surface and is integrally formed as one piece with the first upper surface. The chip disposed on top of the leads comprises a plurality of bumps and a plurality of solders, the coupling protrusions embed into the solders to make the ring surfaces of the coupling protrusions cladded with the solders. The solders cover the first upper surfaces. The chip and the leads are cladded with the molding compound.

    摘要翻译： 半导体封装包括引线框架，至少一个芯片和模塑料。 引线框架包括多个引线，每个引线包括第一端部部分和至少一个联接突出部分，其中第一端部部分包括第一上表面，联接突出部包括环形表面，并且一体地形成为与第 第一上表面。 设置在引线顶部的芯片包括多个凸块和多个焊料，耦合突起嵌入焊料中以使耦合突起的环表面被焊料包覆。 焊料覆盖第一个上表面。 芯片和引线用模塑料包覆。

    SEMICONDUCTOR PACKAGE STRUCTURE
    4.
    发明申请
    SEMICONDUCTOR PACKAGE STRUCTURE 有权
    半导体封装结构

    公开(公告)号：US20130249070A1

    公开(公告)日：2013-09-26

    申请号：US13426804

    申请日：2012-03-22

    申请人： Chin-Tang Hsieh ,  Chih-Ming Kuo ,  Chia-Jung Tu ,  Shih-Chieh Chang ,  Lung-Hua Ho ,  Chih-Hsien Ni

    发明人： Chin-Tang Hsieh ,  Chih-Ming Kuo ,  Chia-Jung Tu ,  Shih-Chieh Chang ,  Lung-Hua Ho ,  Chih-Hsien Ni

    IPC分类号： H01L23/495

    CPC分类号： H01L23/49548 ,  H01L23/3107 ,  H01L23/49582 ,  H01L23/49586 ,  H01L2224/16245

    摘要： A semiconductor package structure comprises a lead frame, at least one chip, a molding compound and an anti-conduction film. The lead frame comprises a plurality of leads, each of the leads comprises a first end portion and a second end portion, wherein the first end portion comprises a first upper surface and a first lower surface, and the second end portion comprises a second upper surface and a second lower surface. The chip comprises a plurality of bumps electrically connected with the lead frame. The chip and the leads are covered with the molding compound. The first lower surface of each of the first end portions and the second lower surface of each of the second end portions are exposed by the molding compound. The first lower surface of the first end portion of each of the leads is covered with the anti-conduction film.

    摘要翻译： 半导体封装结构包括引线框架，至少一个芯片，模塑料和抗导电膜。 引线框架包括多个引线，每个引线包括第一端部和第二端部，其中第一端部包括第一上表面和第一下表面，并且第二端部包括第二上表面 和第二下表面。 芯片包括与引线框电连接的多个凸块。 芯片和引线被模塑料覆盖。 每个第二端部的每个第一端部和第二下表面的第一下表面被模塑料暴露。 每个引线的第一端部的第一下表面被抗导电膜覆盖。

    Semiconductor package structure
    5.
    发明授权
    Semiconductor package structure 有权
    半导体封装结构

    公开(公告)号：US08581384B2

    公开(公告)日：2013-11-12

    申请号：US13426804

    申请日：2012-03-22

    申请人： Chin-Tang Hsieh ,  Chih-Ming Kuo ,  Chia-Jung Tu ,  Shih-Chieh Chang ,  Lung-Hua Ho ,  Chih-Hsien Ni

    发明人： Chin-Tang Hsieh ,  Chih-Ming Kuo ,  Chia-Jung Tu ,  Shih-Chieh Chang ,  Lung-Hua Ho ,  Chih-Hsien Ni

    IPC分类号： H01L23/48

    CPC分类号： H01L23/49548 ,  H01L23/3107 ,  H01L23/49582 ,  H01L23/49586 ,  H01L2224/16245

    摘要： A semiconductor package structure comprises a lead frame, at least one chip, a molding compound and an anti-conduction film. The lead frame comprises a plurality of leads, each of the leads comprises a first end portion and a second end portion, wherein the first end portion comprises a first upper surface and a first lower surface, and the second end portion comprises a second upper surface and a second lower surface. The chip comprises a plurality of bumps electrically connected with the lead frame. The chip and the leads are covered with the molding compound. The first lower surface of each of the first end portions and the second lower surface of each of the second end portions are exposed by the molding compound. The first lower surface of the first end portion of each of the leads is covered with the anti-conduction film.

    摘要翻译： 半导体封装结构包括引线框架，至少一个芯片，模塑料和抗导电膜。 引线框架包括多个引线，每个引线包括第一端部和第二端部，其中第一端部包括第一上表面和第一下表面，并且第二端部包括第二上表面 和第二下表面。 芯片包括与引线框电连接的多个凸块。 芯片和引线被模塑料覆盖。 每个第二端部的每个第一端部和第二下表面的第一下表面被模塑料暴露。 每个引线的第一端部的第一下表面被抗导电膜覆盖。

    Semiconductor package and lead frame thereof
    6.
    发明授权
    Semiconductor package and lead frame thereof 有权
    半导体封装及其引线框架

    公开(公告)号：US08704345B2

    公开(公告)日：2014-04-22

    申请号：US13613309

    申请日：2012-09-13

    申请人： Chih-Ming Kuo ,  Shih-Chieh Chang ,  Chih-Hsien Ni ,  Chin-Tang Hsieh ,  Chia-Jung Tu ,  Lung-Hua Ho

    发明人： Chih-Ming Kuo ,  Shih-Chieh Chang ,  Chih-Hsien Ni ,  Chin-Tang Hsieh ,  Chia-Jung Tu ,  Lung-Hua Ho

    IPC分类号： H01L23/495 ,  H01L23/48

    CPC分类号： H01L24/16 ,  H01L21/4828 ,  H01L23/3107 ,  H01L23/49548 ,  H01L23/49572 ,  H01L23/49582 ,  H01L2224/16245 ,  H01L2924/181 ,  H01L2924/00

    摘要： A semiconductor package includes a lead frame, at least one chip and a molding compound. The lead frame comprises a plurality of leads, each lead comprises a first end portion and at least one coupling protrusion, wherein the first end portion comprises a first upper surface, the coupling protrusion comprises a ring surface and is integrally formed as one piece with the first upper surface. The chip disposed on top of the leads comprises a plurality of bumps and a plurality of solders, the coupling protrusions embed into the solders to make the ring surfaces of the coupling protrusions cladded with the solders. The solders cover the first upper surfaces. The chip and the leads are cladded with the molding compound.

    摘要翻译： 半导体封装包括引线框架，至少一个芯片和模塑料。 引线框架包括多个引线，每个引线包括第一端部部分和至少一个联接突出部分，其中第一端部部分包括第一上表面，联接突出部包括环形表面，并且一体地形成为与第 第一上表面。 设置在引线顶部的芯片包括多个凸块和多个焊料，耦合突起嵌入焊料中以使耦合突起的环表面被焊料包覆。 焊料覆盖第一个上表面。 芯片和引线用模塑料包覆。

    THIN FLIP CHIP PACKAGE STRUCTURE
    7.
    发明申请
    THIN FLIP CHIP PACKAGE STRUCTURE 有权
    薄片芯片包装结构

    公开(公告)号：US20120080783A1

    公开(公告)日：2012-04-05

    申请号：US13163913

    申请日：2011-06-20

    申请人： Chin-Tang Hsieh ,  Rou-Chang Kuo ,  Dueng-Shiu Tzou ,  Chia-Jung Tu ,  Gwo-Shyan Sheu

    发明人： Chin-Tang Hsieh ,  Rou-Chang Kuo ,  Dueng-Shiu Tzou ,  Chia-Jung Tu ,  Gwo-Shyan Sheu

    IPC分类号： H01L23/48

    CPC分类号： H01L23/3677 ,  H01L23/42 ,  H01L24/16 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/15159 ,  H01L2224/0401

    摘要： A thin flip chip package structure comprises a substrate, a chip and a heat dissipation paste, the substrate comprises an insulating layer and a trace layer. The insulating layer comprises a top surface, a bottom surface and a plurality of apertures formed at the bottom surface, wherein the bottom surface of the insulating layer comprises a disposing area and a non-disposing area. Each of the apertures is located at the disposing area and comprises a lateral wall and a base surface. A first thickness is formed between the base surface and the insulating layer, a second thickness is formed between the top surface and the bottom surface, and the second thickness is larger than the first thickness. The chip disposed on the top surface comprises a chip surface and a plurality of bumps. The heat dissipation paste at least fills the apertures and contacts the base surface.

    摘要翻译： 薄的倒装芯片封装结构包括衬底，芯片和散热膏，所述衬底包括绝缘层和迹线层。 绝缘层包括顶表面，底表面和形成在底表面处的多个孔，其中绝缘层的底表面包括布置区域和非布置区域。 每个孔位于设置区域并且包括侧壁和基底表面。 在基面和绝缘层之间形成第一厚度，在顶表面和底表面之间形成第二厚度，第二厚度大于第一厚度。 设置在顶表面上的芯片包括芯片表面和多个凸块。 散热膏至少填充孔并接触基面。

    Thin flip chip package structure
    8.
    发明授权
    Thin flip chip package structure 有权
    薄型倒装芯片封装结构

    公开(公告)号：US08497571B2

    公开(公告)日：2013-07-30

    申请号：US13163913

    申请日：2011-06-20

    申请人： Chin-Tang Hsieh ,  Hou-Chang Kuo ,  Dueng-Shiu Tzou ,  Chia-Jung Tu ,  Gwo-Shyan Sheu

    发明人： Chin-Tang Hsieh ,  Hou-Chang Kuo ,  Dueng-Shiu Tzou ,  Chia-Jung Tu ,  Gwo-Shyan Sheu

    IPC分类号： H01L23/58

    CPC分类号： H01L23/3677 ,  H01L23/42 ,  H01L24/16 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/15159 ,  H01L2224/0401

    摘要： A thin flip chip package structure comprises a substrate, a chip and a heat dissipation paste, the substrate comprises an insulating layer and a trace layer. The insulating layer comprises a top surface, a bottom surface and a plurality of apertures formed at the bottom surface, wherein the bottom surface of the insulating layer comprises a disposing area and a non-disposing area. Each of the apertures is located at the disposing area and comprises a lateral wall and a base surface. A first thickness is formed between the base surface and the insulating layer, a second thickness is formed between the top surface and the bottom surface, and the second thickness is larger than the first thickness. The chip disposed on the top surface comprises a chip surface and a plurality of bumps. The heat dissipation paste at least fills the apertures and contacts the base surface.

    摘要翻译： 薄的倒装芯片封装结构包括衬底，芯片和散热膏，所述衬底包括绝缘层和迹线层。 绝缘层包括顶表面，底表面和形成在底表面处的多个孔，其中绝缘层的底表面包括布置区域和非布置区域。 每个孔位于设置区域并且包括侧壁和基底表面。 在基面和绝缘层之间形成第一厚度，在顶表面和底表面之间形成第二厚度，第二厚度大于第一厚度。 设置在顶表面上的芯片包括芯片表面和多个凸块。 散热膏至少填充孔并接触基面。

    Thin flip chip package structure
    9.
    发明授权
    Thin flip chip package structure 有权
    薄型倒装芯片封装结构

    公开(公告)号：US08471372B2

    公开(公告)日：2013-06-25

    申请号：US13163877

    申请日：2011-06-20

    申请人： Chin-Tang Hsieh ,  Hou-Chang Kuo ,  Dueng-Shiu Tzou ,  Chia-Jung Tu ,  Gwo-Shyan Sheu

    发明人： Chin-Tang Hsieh ,  Hou-Chang Kuo ,  Dueng-Shiu Tzou ,  Chia-Jung Tu ,  Gwo-Shyan Sheu

    IPC分类号： H01L23/495

    CPC分类号： H01L23/13 ,  H01L21/563 ,  H01L23/42 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/00

    摘要： A thin flip chip package structure comprises a substrate, a chip and a heat dissipation paste, wherein the substrate comprises an insulating layer and a trace layer. The insulating layer comprises a first insulating portion and a second insulating portion, the first insulating portion comprises a first upward surface, a first downward surface, a first thickness and a recess formed on the first downward surface, wherein the recess comprises a bottom surface. The second insulating portion comprises a second upward surface, a second downward surface and a second thickness larger than the first thickness. The trace layer is at least formed on the second insulating portion, the chip disposed on top of the substrate is electrically connected with the trace layer and comprises a plurality of bumps, and the heat dissipation paste is disposed at the recess.

    摘要翻译： 薄的倒装芯片封装结构包括衬底，芯片和散热膏，其中衬底包括绝缘层和迹线层。 绝缘层包括第一绝缘部分和第二绝缘部分，第一绝缘部分包括形成在第一下表面上的第一向上表面，第一下表面，第一厚度和凹部，其中凹部包括底表面。 第二绝缘部分包括比第一厚度大的第二向上表面，第二向下表面和第二厚度。 轨迹层至少形成在第二绝缘部分上，设置在基板顶部的芯片与迹线层电连接并且包括多个凸块，并且散热膏设置在凹部处。

    THIN FLIP CHIP PACKAGE STRUCTURE
    10.
    发明申请
    THIN FLIP CHIP PACKAGE STRUCTURE 有权
    薄片芯片包装结构

    公开(公告)号：US20120074545A1

    公开(公告)日：2012-03-29

    申请号：US13163877

    申请日：2011-06-20

    申请人： Chin-Tang Hsieh ,  Hou-Chang Kuo ,  Dueng-Shiu Tzou ,  Chia-Jung Tu ,  Gwo-Shyan Sheu

    发明人： Chin-Tang Hsieh ,  Hou-Chang Kuo ,  Dueng-Shiu Tzou ,  Chia-Jung Tu ,  Gwo-Shyan Sheu

    IPC分类号： H01L23/495

    CPC分类号： H01L23/13 ,  H01L21/563 ,  H01L23/42 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/00

    摘要： A thin flip chip package structure comprises a substrate, a chip and a heat dissipation paste, wherein the substrate comprises an insulating layer and a trace layer. The insulating layer comprises a first insulating portion and a second insulating portion, the first insulating portion comprises a first upward surface, a first downward surface, a first thickness and a recess formed on the first downward surface, wherein the recess comprises a bottom surface. The second insulating portion comprises a second upward surface, a second downward surface and a second thickness larger than the first thickness. The trace layer is at least formed on the second insulating portion, the chip disposed on top of the substrate is electrically connected with the trace layer and comprises a plurality of bumps, and the heat dissipation paste is disposed at the recess.

    摘要翻译： 薄的倒装芯片封装结构包括衬底，芯片和散热膏，其中衬底包括绝缘层和迹线层。 绝缘层包括第一绝缘部分和第二绝缘部分，第一绝缘部分包括形成在第一下表面上的第一向上表面，第一下表面，第一厚度和凹部，其中凹部包括底表面。 第二绝缘部分包括比第一厚度大的第二向上表面，第二向下表面和第二厚度。 轨迹层至少形成在第二绝缘部分上，设置在基板顶部的芯片与迹线层电连接并且包括多个凸块，并且散热膏设置在凹部处。