公开(公告)号：US06388319B1

公开(公告)日：2002-05-14

申请号：US09577867

申请日：2000-05-24

申请人： Chuan Cheah ,  Naresh Thapar ,  Srini Thiruvenkatachari

发明人： Chuan Cheah ,  Naresh Thapar ,  Srini Thiruvenkatachari

IPC分类号： H01L2334

CPC分类号： H01L23/49562 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/0603 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48739 ,  H01L2224/48744 ,  H01L2224/49111 ,  H01L2224/85205 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12032 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device includes: at least first, second, and third semiconductor dice, each having opposing surfaces which contain respective electrodes; a conductive lead frame including first and second separate die pad areas, the first and second semiconductor dice being disposed on the first die pad, and the third semiconductor die being disposed on the second die pad; a first plurality of pins being integral with and extending from one edge of the first die pad; a second plurality of pins being integral with and extending from one edge of the second die pad; a third plurality of pins being separated from one another and from the first and second die pads; a first plurality of bonding wires connecting one surface of the first semiconductor die to at least one of the third plurality of pins; a second plurality of bonding wires connecting one surface of the third semiconductor die to at least another one of the third plurality of pins; and a housing for encapsulating the lead frame, semiconductor dice, and bonding wires, the first, second and third pluralities of pins extending beyond a periphery of the housing for external connection.

摘要翻译： 半导体器件包括：至少第一，第二和第三半导体管芯，每个具有包含相应电极的相对表面; 导电引线框架，包括第一和第二单独的管芯焊盘区域，第一和第二半导体管芯设置在第一管芯焊盘上，第三半导体管芯设置在第二管芯焊盘上; 第一多个销与第一管芯焊盘的一个边缘成一体并从其延伸; 与所述第二管芯焊盘的一个边缘成一体并从所述第二管芯焊盘的一个边缘延伸的第二多个引脚; 第三多个引脚彼此分离并且与第一和第二管芯焊盘分离; 将所述第一半导体管芯的一个表面连接到所述第三多个引脚中的至少一个的第一多个接合线; 将第三半导体管芯的一个表面连接到第三多个引脚中的至少另一个引脚的第二多个接合线; 以及用于封装引线框架，半导体管芯和接合线的壳体，所述第一，第二和第三多个销延伸超出所述外壳的周边以用于外部连接。

公开(公告)号：US06448643B2

公开(公告)日：2002-09-10

申请号：US09812464

申请日：2001-03-20

申请人： Chuan Cheah ,  Naresh Thapar ,  Srini Thiruvenkatachari

发明人： Chuan Cheah ,  Naresh Thapar ,  Srini Thiruvenkatachari

IPC分类号： H01L2334

CPC分类号： H01L23/49575 ,  H01L23/49562 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/0603 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/85207 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01047 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12032 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： An SO-8 type package contains a control MOSFET die mounted on one lead frame section and a synchronous MOSFET and Schottky diode die is mounted on a second lead frame pad section. The die are interconnected through the lead frame pads and wire bonds to define a buck converter circuit and the die and lead frame pads are overmolded with a common insulation housing.

摘要翻译： SO-8型封装包含安装在一个引线框架部分上的控制MOSFET管芯，并且同步MOSFET和肖特基二极管管芯安装在第二引线框架焊盘部分上。 管芯通过引线框架焊盘和引线接合互连，以定义降压转换器电路，并且模具和引线框架焊盘用共同的绝缘外壳包覆成型。

公开(公告)号：US07557395B2

公开(公告)日：2009-07-07

申请号：US10766465

申请日：2004-01-27

申请人： Ling Ma ,  Adam Amali ,  Siddharth Kiyawat ,  Ashita Mirchandani ,  Donald He ,  Naresh Thapar ,  Ritu Sodhi ,  Kyle Spring ,  Daniel Kinzer

发明人： Ling Ma ,  Adam Amali ,  Siddharth Kiyawat ,  Ashita Mirchandani ,  Donald He ,  Naresh Thapar ,  Ritu Sodhi ,  Kyle Spring ,  Daniel Kinzer

IPC分类号： H01L29/76

CPC分类号： H01L29/7813 ,  H01L29/0661 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811 ,  H02M3/1588 ,  Y02B70/1466 ,  Y10S257/901

摘要： A trench power semiconductor device including a recessed termination structure.

摘要翻译： 一种沟槽功率半导体器件，包括凹入的端接结构。

公开(公告)号：US07485932B2

公开(公告)日：2009-02-03

申请号：US11185319

申请日：2005-07-20

申请人： Naresh Thapar

发明人： Naresh Thapar

IPC分类号： H01L29/80

CPC分类号： H01L29/7828 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/7839

摘要： An accumulation mode FET (ACCUFET) which includes an insulated gate, an adjacently disposed insulated source field electrode, and a source contact that makes Schottky contact with the base region of the ACCUFET.

摘要翻译： 一种累积模式FET（ACCUFET），其包括绝缘栅极，相邻设置的绝缘源场电极和使得与ACCUFET的基极区域肖特基接触的源极接触。

公开(公告)号：US07397083B2

公开(公告)日：2008-07-08

申请号：US11982815

申请日：2007-11-05

申请人： Adam I Amali ,  Naresh Thapar

发明人： Adam I Amali ,  Naresh Thapar

IPC分类号： H01L29/76

CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/4933 ,  H01L29/66734 ,  H01L29/7811

摘要： A trench type power MOSgated device has a plurality of spaced trenches lined with oxide and filled with conductive polysilicon. The tops of the polysilicon fillers are below the top silicon surface and are capped with a deposited oxide the top of which is flush with the top of the silicon. Source regions of short lateral extent extend into the trench walls to a depth below the top of the polysilicon. A trench termination is formed having an insulation oxide liner covered by a polysilicon layer, covered in turn by a deposited oxide.

摘要翻译： 沟槽型功率MOS器件具有衬有氧化物并填充有导电多晶硅的多个隔开的沟槽。 多晶硅填料的顶部位于顶部硅表面之下，并用沉积的氧化物封盖，其顶部与硅的顶部齐平。 短横向范围的源区域延伸到沟槽壁中至多晶硅顶部的深度。 形成具有由多晶硅层覆盖的绝缘氧化物衬垫的沟槽端接，并且依次由被沉积的氧化物覆盖。

公开(公告)号：US20060017078A1

公开(公告)日：2006-01-26

申请号：US11185319

申请日：2005-07-20

申请人： Naresh Thapar

发明人： Naresh Thapar

IPC分类号： H01L29/80

CPC分类号： H01L29/7828 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/7839

摘要： An accumulation mode FET (ACCUFET) which includes an insulated gate, an adjacently disposed insulated source field electrode, and a source contact that makes Schottky contact with the base region of the ACCUFET.

公开(公告)号：US20120235209A1

公开(公告)日：2012-09-20

申请号：US13288500

申请日：2011-11-03

申请人： Michael A. Briere ,  Naresh Thapar

发明人： Michael A. Briere ,  Naresh Thapar

IPC分类号： H01L29/778 ,  H01L27/088

CPC分类号： H01L29/7786 ,  H01L27/0605 ,  H01L27/0629 ,  H01L29/2003 ,  H01L29/42364 ,  H02M7/106

摘要： According to one exemplary embodiment, a rectifier circuit includes a diode. A first depletion-mode transistor is connected to a cathode of the diode. Also, at least one second depletion-mode transistor is in parallel with the first depletion-mode transistor and is configured to supply a pre-determined current range to a cathode of the diode. A pinch off voltage of the at least one second depletion-mode transistor can be more negative than a pinch off voltage of the first depletion-mode transistor and the at least one second depletion-mode transistor can be configured to supply the pre-determined current range while the first depletion-mode transistor is OFF. Also, the pre-determined current range can be greater than a leakage current of the first depletion-mode transistor.

摘要翻译： 根据一个示例性实施例，整流器电路包括二极管。 第一耗尽型晶体管连接到二极管的阴极。 此外，至少一个第二耗尽型晶体管与第一耗尽型晶体管并联并且被配置为向二极管的阴极提供预定电流范围。 至少一个第二耗尽型晶体管的截止电压可以比第一耗尽型晶体管的夹断电压更负，并且至少一个第二耗尽型晶体管可以被配置为提供预定电流 而第一耗尽型晶体管为OFF时。 此外，预定电流范围可以大于第一耗尽型晶体管的漏电流。

公开(公告)号：US07999310B2

公开(公告)日：2011-08-16

申请号：US12172802

申请日：2008-07-14

申请人： Naresh Thapar

发明人： Naresh Thapar

IPC分类号： H01L29/66

CPC分类号： H01L29/7828 ,  H01L29/407 ,  H01L29/41741 ,  H01L2924/0002 ,  H01L2924/00

摘要： An accumulation mode FET (ACCUFET) having a source contact that makes Schottky contact with the base region thereof.

摘要翻译： 具有与其基极区域进行肖特基接触的源极接触的累积模式FET（ACCUFET）。

公开(公告)号：US20080061365A1

公开(公告)日：2008-03-13

申请号：US11982815

申请日：2007-11-05

申请人： Adam Amali ,  Naresh Thapar

发明人： Adam Amali ,  Naresh Thapar

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/4933 ,  H01L29/66734 ,  H01L29/7811

摘要： A trench type power MOSgated device has a plurality of spaced trenches lined with oxide and filled with conductive polysilicon. The tops of the polysilicon fillers are below the top silicon surface and are capped with a deposited oxide the top of which is flush with the top of the silicon. Source regions of short lateral extent extend into the trench walls to a depth below the top of the polysilicon. A trench termination is formed having an insulation oxide liner covered by a polysilicon layer, covered in turn by a deposited oxide.

公开(公告)号：US07482654B2

公开(公告)日：2009-01-27

申请号：US11110467

申请日：2005-04-20

申请人： Jianjun Cao ,  Timothy D. Henson ,  Naresh Thapar ,  Paul Harvey ,  David Kent

发明人： Jianjun Cao ,  Timothy D. Henson ,  Naresh Thapar ,  Paul Harvey ,  David Kent

IPC分类号： H01L29/76

CPC分类号： H01L29/7828 ,  H01L29/407 ,  H01L29/66666

摘要： A power semiconductor device which includes a source field electrode, and at least one insulated gate electrode adjacent a respective side of the source field electrode, the source field electrode and the gate electrode being disposed in a common trench, and a method for fabricating the device.

摘要翻译： 一种功率半导体器件，包括源极电极和邻近源极场电极的相应侧的至少一个绝缘栅电极，源极场电极和栅电极设置在公共沟槽中，以及制造该器件的方法 。