Combinable power socket system
    1.
    发明授权

    公开(公告)号:US10256664B2

    公开(公告)日:2019-04-09

    申请号:US15346718

    申请日:2016-11-08

    IPC分类号: H02J7/00 H02M7/04 H02J13/00

    摘要: An intelligent power socket system is disclosed. The system is composed of a control module, a switched electricity receptacle module, a switched USB module and a dimming receptacle module. Each module has a power plug and a power socket. The control module can receive control commands from a smartphone by a user. The other three functional modules can be controlled by the control module through power line communication (PLC). The modules may be located at different places within an electricity supply division so that they can communicate through the power lines.

    SYSTEM FOR TRANSFERRING ELECTRIC POWER AND SIGNALS VIA POWER LINE BY TIME-DIVISION MULTIPLEXING
    2.
    发明申请
    SYSTEM FOR TRANSFERRING ELECTRIC POWER AND SIGNALS VIA POWER LINE BY TIME-DIVISION MULTIPLEXING 审中-公开
    用于通过时分复用技术通过电源线传输电力和信号的系统

    公开(公告)号:US20130100966A1

    公开(公告)日:2013-04-25

    申请号:US13308611

    申请日:2011-12-01

    IPC分类号: H04J3/06

    摘要: A system for transferring electric power and signals via a power line by time-division multiplexing includes a power line, electronic-circuit units, and controllers. The power line includes a first transmission line and a second transmission line. The first transmission line is connected with a first switch in series and is therefore divided into a source end and a loading end. The electronic-circuit units are connected in series between the loading end and the second transmission line. The controllers are electrically connected with and are configured for synchronously controlling the first switch and the electronic-circuit units. When the first switch is closed, electric power is transferred from an electric power source to the loading end, and when the first switch is opened, the electronic-circuit units transfer signals via the loading end. The system features simple circuitry and effectively reduces noise in signal transmission.

    摘要翻译: 通过时分复用通过电力线传送电力和信号的系统包括电力线,电子电路单元和控制器。 电力线包括第一传输线和第二传输线。 第一传输线与第一开关串联连接,因此被分为源端和负载端。 电子电路单元串联连接在负载端和第二传输线之间。 控制器与第一开关和电子电路单元电连接并被构造成用于同步地控制第一开关和电子电路单元。 当第一开关闭合时,电力从电源传送到装载端,并且当第一开关打开时,电子电路单元经由装载端传送信号。 该系统具有简单的电路,有效降低信号传输中的噪声。

    WATER LEVEL MONITORING SYSTEM
    4.
    发明申请

    公开(公告)号:US20190101428A1

    公开(公告)日:2019-04-04

    申请号:US15821837

    申请日:2017-11-23

    IPC分类号: G01F23/00

    摘要: A water level monitoring system includes at least one floating unit, a load cell and a sensor module. The floating unit is used for sinking in water. The load cell is connected to the floating unit for generating a force value reflecting buoyancy generating from the floating unit entering the water. The sensor module is connected to the load cell for sensing the force value from the load cell and includes an amplifier for amplifying a sensed value. A processor connected to the amplifier receives the sensed value from the amplifier and calculating a water level depth to be measured. Thus the water level motoring system has features of low cost, high stability and flexibility.

    CHIP STRUCTURE HAVING HISTORY RECORDING UNIT
    5.
    发明申请
    CHIP STRUCTURE HAVING HISTORY RECORDING UNIT 审中-公开
    具有历史记录单元的芯片结构

    公开(公告)号:US20130110465A1

    公开(公告)日:2013-05-02

    申请号:US13312219

    申请日:2011-12-06

    IPC分类号: G06F17/40

    CPC分类号: G01R31/2856 G01R31/31707

    摘要: A chip structure having a history recording unit is provided. The chip structure includes a core circuit unit in addition to the history recording unit. The history recording unit includes a sensing unit, a record unit, and a deliver unit. The sensing unit detects the status of the core circuit unit and generates history information accordingly. The history information is saved into the record unit and can be further output by the deliver unit. Thus, the history information of the chip structure can be recorded and effectively used to eliminate the reliability problem of the chip structure.

    摘要翻译: 提供具有历史记录单元的芯片结构。 除了历史记录单元之外,芯片结构还包括核心电路单元。 历史记录单元包括感测单元,记录单元和传送单元。 感测单元检测核心电路单元的状态并相应地生成历史信息。 历史信息被保存到记录单元中,并且可以由传送单元进一步输出。 因此,可以记录和有效地利用芯片结构的历史信息来消除芯片结构的可靠性问题。

    Socket structure stack and socket structure thereof
    6.
    发明授权
    Socket structure stack and socket structure thereof 有权
    套接字结构堆栈和套接字结构

    公开(公告)号:US08172622B1

    公开(公告)日:2012-05-08

    申请号:US13183595

    申请日:2011-07-15

    IPC分类号: H01R13/502

    摘要: A socket structure stack and a socket structure thereof are provided. The socket structure stack includes at least two socket structures, and each socket structure includes a main body, a plurality of conductive elements, and a plurality of connecting elements. The main body includes an inner plate and an outer plate, wherein the inner plate has a receiving portion and an embedded portion. The conductive elements are embedded in the embedded portion, and the connecting elements are mounted on the outer plate so as to connect adjacent socket structures together. The socket structures are so configured that ICs, processors, and printed circuit boards connected to the socket structures or the socket structures themselves can be recycled. Moreover, the printed circuit boards can be easily assembled to the socket structures, and the socket structures can be stacked up and securely connected to form a 3D structure which is otherwise difficult to put together by soldering.

    摘要翻译: 提供了一种插座结构堆叠及其插座结构。 插座结构堆叠包括至少两个插座结构,并且每个插座结构包括主体,多个导电元件和多个连接元件。 主体包括内板和外板,其中内板具有接收部分和嵌入部分。 导电元件嵌入在嵌入部分中,并且连接元件安装在外板上,以将相邻的插座结构连接在一起。 插座结构被配置成使得连接到插座结构或插座结构本身的IC,处理器和印刷电路板可以被再循环。 此外,印刷电路板可以容易地组装到插座结构上,并且插座结构可以堆叠并牢固地连接以形成否则难以通过焊接放在一起的3D结构。

    DEVICE INCLUDING A VIRTUAL DRIVE SYSTEM
    7.
    发明申请
    DEVICE INCLUDING A VIRTUAL DRIVE SYSTEM 审中-公开
    设备包括虚拟驱动系统

    公开(公告)号:US20110282831A1

    公开(公告)日:2011-11-17

    申请号:US12821163

    申请日:2010-06-23

    IPC分类号: G06F17/30 G06F7/00

    CPC分类号: G06F9/4411

    摘要: A device including a virtual drive system is provided. An image file can be identified as an ordinary physical disk drive via the device. The device includes a storage unit, an image management unit, and an operating-system interface. The storage unit is configured to store at least one image file. The image management unit includes an image management program which can manage the image files to be selected. The operating-system interface is connected by electrical signals with an operating-system apparatus and is controlled by the image management program to send a controlling signal to the operating-system apparatus. Therefore, the operating-system apparatus can identify as many physical disk drives as the corresponding selected image files.

    摘要翻译: 提供了包括虚拟驱动系统的设备。 图像文件可以通过该设备被识别为普通的物理磁盘驱动器。 该设备包括存储单元,图像管理单元和操作系统接口。 存储单元被配置为存储至少一个图像文件。 图像管理单元包括能够管理要选择的图像文件的图像管理程序。 操作系统接口通过电信号与操作系统装置连接,并由图像管理程序控制,以将控制信号发送到操作系统装置。 因此,操作系统设备可以识别与相应的所选图像文件一样多的物理磁盘驱动器。

    THREE-DIMENSIONAL SOC STRUCTURE FORMED BY STACKING MULTIPLE CHIP MODULES
    8.
    发明申请
    THREE-DIMENSIONAL SOC STRUCTURE FORMED BY STACKING MULTIPLE CHIP MODULES 有权
    通过堆叠多个芯片模块形成的三维SOC结构

    公开(公告)号:US20110188210A1

    公开(公告)日:2011-08-04

    申请号:US12752345

    申请日:2010-04-01

    IPC分类号: H05K1/14 H05K7/00

    摘要: A three-dimensional SoC structure formed by stacking multiple chip modules is provided. The three-dimensional SoC structure includes at least two vertical SoC modules and at least one connector module, wherein each connector module electrically connects two vertical SoC modules. Each vertical SoC module is constructed by stacking at least two chip modules vertically. Each chip module includes a module circuit board and at least one preset element. A recess is formed in each module circuit board and provided with a first connecting interface for electrically connecting with the corresponding at least one preset element. The at least two vertical SoC modules are connected by the connector module to form a three-dimensional SoC structure with multiple functions. Besides, the recesses formed in the module circuit boards provide effective heat dissipation paths for the preset elements.

    摘要翻译: 提供了通过堆叠多个芯片模块形成的三维SoC结构。 三维SoC结构包括至少两个垂直SoC模块和至少一个连接器模块,其中每个连接器模块电连接两个垂直SoC模块。 每个垂直SoC模块通过垂直堆叠至少两个芯片模块构成。 每个芯片模块包括模块电路板和至少一个预设元件。 在每个模块电路板中形成凹部,并设置有用于与相应的至少一个预设元件电连接的第一连接接口。 至少两个垂直SoC模块通过连接器模块连接,形成具有多种功能的三维SoC结构。 此外,形成在模块电路板中的凹部为预设元件提供有效的散热路径。

    Vehicle idle-speed warning system and idle-speed detection method
    9.
    发明授权
    Vehicle idle-speed warning system and idle-speed detection method 有权
    车辆怠速预警系统和怠速检测方法

    公开(公告)号:US09291115B2

    公开(公告)日:2016-03-22

    申请号:US13594615

    申请日:2012-08-24

    摘要: A vehicle idle-speed warning system and vehicle idle-speed detection method thereof are provided. It is non-invasive, that is, there is no need to change or modify any part of the constructing parts in the engine compartment. The present invention can be adopted stand-alone, or be applied to existing popular apparatuses, such as GPS, driving recorders, smart handheld devices, and vehicle electronic equipments. With the composing elements of a motion information module, an input module, an output module, a timer module and an information processing module, the present invention can accurately determine whether the vehicle under surveillance is in idle state and for how long it is in the idle state, and send an alarm signal automatically. With the implementation of the present invention, drivers can always be alarmed with the vehicle idling situations to prevent possible dangers or coming tickets due to the violation of traffic regulations in certain countries.

    摘要翻译: 提供了一种车辆怠速预警系统和车辆怠速检测方法。 这是非侵入性的,也就是说,不需要更改或修改发动机舱中构造部件的任何部分。 本发明可以单独使用,也可以应用于GPS,驾驶记录器,智能手持装置,车载电子设备等现有的流行装置。 利用运动信息模块,输入模块,输出模块,定时器模块和信息处理模块的组成元件,本发明可以准确地确定被监视的车辆是否处于空闲状态以及在多长时间内 空闲状态,并自动发送报警信号。 随着本发明的实施,驾驶员总是可以用车辆空转情况来警惕,以防止在某些国家因违反交通规则而导致的可能的危险或来车。

    Virtualized Peripheral Hardware Platform System
    10.
    发明申请
    Virtualized Peripheral Hardware Platform System 审中-公开
    虚拟化外设硬件平台系统

    公开(公告)号:US20120102254A1

    公开(公告)日:2012-04-26

    申请号:US12961783

    申请日:2010-12-07

    IPC分类号: G06F13/20

    CPC分类号: G06F13/385 G06F2213/0058

    摘要: The present invention discloses a virtualized peripheral hardware platform system. The virtualized peripheral hardware platform system includes a first hardware platform and a software platform, which is executed in a second hardware platform. The first hardware platform is in signal communication with the second hardware platform. The software platform not only simulates the operation of the peripheral device of the first hardware platform but also simulates input signals of virtual peripheral devices and then transmits the input signals to the first hardware platform to conduct further calculations. Furthermore, the input/output (I/O) interface of the second hardware platform can be simulated as the I/O interface of the first hardware platform, so as to decrease the number of the I/O interface which the first hardware platform needed and downsize the first hardware platform.

    摘要翻译: 本发明公开了一种虚拟化的外围硬件平台系统。 虚拟化外设硬件平台系统包括第一个硬件平台和一个在第二个硬件平台上执行的软件平台。 第一个硬件平台与第二个硬件平台进行信号通信。 该软件平台不仅模拟第一硬件平台的外围设备的运行,而且模拟虚拟外围设备的输入信号,然后将输入信号发送到第一硬件平台进行进一步的计算。 此外,可以将第二硬件平台的输入/输出(I / O)接口模拟为第一硬件平台的I / O接口,从而减少第一硬件平台所需的I / O接口数量 并缩小了第一个硬件平台。