公开(公告)号：US20100283141A1

公开(公告)日：2010-11-11

申请号：US12463431

申请日：2009-05-11

申请人： Chun-Wei Chang ,  Tung-Hsien Hsieh ,  Chia-Hui Liu

发明人： Chun-Wei Chang ,  Tung-Hsien Hsieh ,  Chia-Hui Liu

IPC分类号： H01L23/49

CPC分类号： H01L23/49541 ,  H01L23/3107 ,  H01L23/49582 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/48644 ,  H01L2224/48664 ,  H01L2224/85444 ,  H01L2224/85464 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor chip package includes a chip; first and second connection pads arranged in a matrix and disposed about the chip, and the first and second connection pads have different bottom surface shapes when viewed from a bottom of the QFN package; bonding pads provided on an active surface of the chip and being electrically connected with corresponding said connection pads through bonding wires; and a package body encapsulating the chip, the bonding wires and an upper portion of each of the connection pads such that a lower portion of each of the connection pads extends outward from a bottom of the package body.

摘要翻译： 半导体芯片封装包括芯片; 第一和第二连接焊盘，其布置成矩阵并围绕芯片设置，并且当从QFN封装的底部观察时，第一和第二连接焊盘具有不同的底表面形状; 接合焊盘，设置在芯片的有源表面上，并通过接合线与对应的所述连接焊盘电连接; 以及封装体，其包封芯片，接合线和每个连接焊盘的上部，使得每个连接焊盘的下部从封装主体的底部向外延伸。

公开(公告)号：US09244458B2

公开(公告)日：2016-01-26

申请号：US13354548

申请日：2012-01-20

申请人： Wen-Yuh Jywe ,  Tung-Hsien Hsieh ,  Chia-Hung Chen ,  Chin-Hui Huang ,  Ying-Chien Tsai ,  Yen-Chieh Wang

发明人： Wen-Yuh Jywe ,  Tung-Hsien Hsieh ,  Chia-Hung Chen ,  Chin-Hui Huang ,  Ying-Chien Tsai ,  Yen-Chieh Wang

IPC分类号： G05B19/4097

CPC分类号： G05B19/4097 ,  G05B2219/49084

摘要： A method of numerical-control scraping of a work piece has a preparing step, a scanning step, a flatness-parameter inputting step, a surface-finishing step, a related-parameter inputting step, an auto-scraping step and an analyzing step. The preparing step comprises preparing a multi-axis machine tool, a laser displacement meter, an auto scraping apparatus and a computer. The scanning step comprises scanning the work piece. The flatness-parameter inputting step comprises inputting a flatness-parameter. The surface-finishing step comprises calculating out the to-be-scraped ranges of the work piece and scraping the work piece. The related-parameter inputting step comprises inputting desired PPI and POP in the computer, calculating out the HOP, the DOS and the oil content to obtain the length, the width and the depth of a single scraping process. The auto-scraping step comprises scraping the work piece to meet the requirement. The analyzing step comprises detecting the 3D-appearance drawing of the work piece.

摘要翻译： 一种数控刮削工件的方法具有准备步骤，扫描步骤，平坦度参数输入步骤，表面精加工步骤，相关参数输入步骤，自动刮除步骤和分析步骤。 制备步骤包括制备多轴机床，激光位移计，自动刮除装置和计算机。 扫描步骤包括扫描工件。 平坦度参数输入步骤包括输入平坦度参数。 表面精加工步骤包括计算工件的被刮削范围并刮擦工件。 相关参数输入步骤包括在计算机中输入所需的PPI和POP，计算出HOP，DOS和油含量，以获得单次刮除过程的长度，宽度和深度。 自动刮削步骤包括刮擦工件以满足要求。 分析步骤包括检测工件的3D外观图。

公开(公告)号：US20100213589A1

公开(公告)日：2010-08-26

申请号：US12704517

申请日：2010-02-11

申请人： Tung-Hsien Hsieh

发明人： Tung-Hsien Hsieh

IPC分类号： H01L23/495 ,  H01L21/60

CPC分类号： H01L23/5389 ,  H01L21/4832 ,  H01L23/3107 ,  H01L23/3135 ,  H01L23/49503 ,  H01L23/49531 ,  H01L23/49548 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/19 ,  H01L24/28 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/91 ,  H01L24/92 ,  H01L25/03 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05554 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/20 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/078 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A multi-chip package includes a chip carrier; a semiconductor die mounted on a die attach surface of the chip carrier, wherein a plurality of input/output (I/O) pads are situated in or on the semiconductor die; a rewiring laminate structure on the semiconductor die, the rewiring laminate structure comprising a plurality of redistribution pads for the I/O pads; at least one bond wire interconnecting at least one of the redistribution pads with the chip carrier; a chip package mounted on at least another of the redistribution pads; and a mold cap encapsulating at least a portion of the bond wire.

摘要翻译： 多芯片封装包括芯片载体; 安装在所述芯片载体的管芯附着表面上的半导体管芯，其中多个输入/输出（I / O）焊盘位于所述半导体管芯中或所述半导体管芯上; 在所述半导体管芯上的再布线层压结构，所述重新布线层压结构包括用于所述I / O焊盘的多个再分配焊盘; 将所述再分配焊盘中的至少一个与所述芯片载体互连的至少一个接合线; 安装在至少另一个再分配垫上的芯片封装; 以及封装所述接合线的至少一部分的模具盖。

公开(公告)号：US20100060906A1

公开(公告)日：2010-03-11

申请号：US12206026

申请日：2008-09-08

申请人： Wen-Yuh Jywe ,  Chien-Hung Liu ,  Yi-Tsung Li ,  Tung-Hsien Hsieh ,  Tung-Hui Hsu ,  Hung-Shu Wang

发明人： Wen-Yuh Jywe ,  Chien-Hung Liu ,  Yi-Tsung Li ,  Tung-Hsien Hsieh ,  Tung-Hui Hsu ,  Hung-Shu Wang

IPC分类号： G01B11/00

CPC分类号： G01B11/272 ,  B23Q17/24 ,  B23Q2230/002

摘要： Means for measuring a working machine's structural deviation from five reference axes includes a main sensing body bonded with a main axis of the working machine (or controlled to revolve), and a lighting unit set around the main sensing body to circle about the main sensing body with a fixed radius (or the lighting unit radiates a light on the main sensing body from that radial distance and circles along with the main sensing body) such that as soon as the main sensing body has detected an optical signal, it is converted to an error signal informing of the working machine's structural deviation in two or three dimensional displacement.

摘要翻译： 用于测量工作机械与五个参考轴的结构偏差的装置包括与工作机的主轴（或控制旋转）结合的主感测体，以及围绕主感测体围绕主感测体环绕的照明单元 具有固定半径（或者照明单元从该径向距离辐射主感测体上的光并与主感测体一起旋转），使得一旦主感测体检测到光信号，就将其转换为 误差信号通知工作机械在二维或三维位移中的结构偏差。

公开(公告)号：US08288870B2

公开(公告)日：2012-10-16

申请号：US12880859

申请日：2010-09-13

申请人： Tung-Hsien Hsieh

发明人： Tung-Hsien Hsieh

IPC分类号： H01L23/22 ,  H01L23/24 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/49838 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/15311 ,  H05K1/114 ,  H05K3/242 ,  H05K2201/09709 ,  H05K2201/10734 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A semiconductor chip package is disclosed. The semiconductor chip package comprises a package substrate having a bottom surface. At least four adjacent ball pads are on the bottom surface, arranged in a first two-row array along a first direction and a second direction. At least four vias are drilled through the package substrate, arranged in a second two-row array, wherein each of the vias in a row of the second two-row array is offset by a first distance along the first direction and a second distance along the second direction from the connecting ball pads in a row of the first two-row array, and each of the vias in the other adjacent row of the second two-row array is offset by the first distance along an opposite direction to the first direction and the second distance along the second direction from the connecting ball pads in the other adjacent row of the first two-row array.

摘要翻译： 公开了半导体芯片封装。 半导体芯片封装包括具有底表面的封装衬底。 至少四个相邻的球垫位于底表面上，沿着第一方向和第二方向布置在第一两列阵列中。 至少四个通孔穿过封装衬底，布置在第二两列阵列中，其中第二两列阵列的一排中的每个通孔偏移沿着第一方向的第一距离和沿第一方向的第二距离 来自第一两列阵列的一行中的连接球焊盘的第二方向，并且第二两列阵列的另一相邻行中的每个通孔沿与第一方向相反的方向偏移第一距离 以及沿着第二方向从第一两列阵列的另一相邻行中的连接球焊盘的第二距离。

公开(公告)号：US20110074008A1

公开(公告)日：2011-03-31

申请号：US12621505

申请日：2009-11-19

申请人： Tung-Hsien Hsieh

发明人： Tung-Hsien Hsieh

IPC分类号： H01L23/48

CPC分类号： H01L23/5382 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/19107

摘要： This invention provides a semiconductor flip chip package including a carrier substrate and a flip chip mounted on the carrier substrate. The flip chip comprises a first input/output (I/O) pad and a second I/O pad on an active surface of the flip chip, wherein a switching between the first I/O pad and the second I/O pad is implemented by wire bonding.

摘要翻译： 本发明提供一种半导体倒装芯片封装，其包括载体基板和安装在载体基板上的倒装芯片。 倒装芯片包括倒装芯片的有源表面上的第一输入/输出（I / O）焊盘和第二I / O焊盘，其中实现第一I / O焊盘和第二I / O焊盘之间的切换 通过引线键合。

公开(公告)号：US07786557B2

公开(公告)日：2010-08-31

申请号：US12390492

申请日：2009-02-22

申请人： Tung-Hsien Hsieh ,  Nan-Cheng Chen

发明人： Tung-Hsien Hsieh ,  Nan-Cheng Chen

IPC分类号： H01L23/495

CPC分类号： H01L23/3107 ,  H01L21/4832 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49586 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/4911 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19042 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A quad flat non-lead (QFN) semiconductor package includes a die attach pad having a recessed area; a semiconductor die mounted inside the recessed area of the die attach pad; at least one row of inner terminal leads disposed adjacent to the die attach pad; first wires bonding respective said inner terminal leads to the semiconductor die; at least one row of extended, outer terminal leads disposed along periphery of the QFN semiconductor package; at least one row of intermediary terminals disposed between the inner terminal leads and the extended, outer terminal leads; second wires bonding respective the intermediary terminals to the semiconductor die; and third wires bonding respective the intermediary terminals to the extended, outer terminal leads.

摘要翻译： 四边形非引线（QFN）半导体封装包括具有凹陷区域的管芯附接焊盘; 安装在管芯附接垫的凹陷区域内的半导体管芯; 至少一列内部端子引线邻近管芯附接垫设置; 将所述内部端子引线分别连接到所述半导体管芯的第一引线; 至少一排沿QFN半导体封装的周边设置的延伸外端子引线; 设置在内部端子引线和延伸的外部端子引线之间的至少一排中间端子; 将所述中间端子分别连接到所述半导体管芯的第二配线; 以及将中间端子分别连接到扩展的外部端子引线的第三线。

公开(公告)号：US20130190912A1

公开(公告)日：2013-07-25

申请号：US13354548

申请日：2012-01-20

申请人： Wen-Yuh JYWE ,  Tung-Hsien Hsieh ,  Chia-Hung Chen ,  Chin - Hui Huang ,  Ying-Chien Tsai ,  Yen-Chieh Wang

发明人： Wen-Yuh JYWE ,  Tung-Hsien Hsieh ,  Chia-Hung Chen ,  Chin - Hui Huang ,  Ying-Chien Tsai ,  Yen-Chieh Wang

IPC分类号： G05B19/4097

CPC分类号： G05B19/4097 ,  G05B2219/49084

摘要： A method of numerical-control scraping of a work piece has a preparing step, a scanning step, a flatness-parameter inputting step, a surface-finishing step, a related-parameter inputting step, an auto-scraping step and an analyzing step. The preparing step comprises preparing a multi-axis machine tool, a laser displacement meter, an auto scraping apparatus and a computer. The scanning step comprises scanning the work piece. The flatness-parameter inputting step comprises inputting a flatness-parameter. The surface-finishing step comprises calculating out the to-be-scraped ranges of the work piece and scraping the work piece. The related-parameter inputting step comprises inputting desired PPI and POP in the computer, calculating out the HOP, the DOS and the oil content to obtain the length, the width and the depth of a single scraping process. The auto-scraping step comprises scraping the work piece to meet the requirement. The analyzing step comprises detecting the 3D-appearance drawing of the work piece.

摘要翻译： 一种数控刮削工件的方法具有准备步骤，扫描步骤，平坦度参数输入步骤，表面精加工步骤，相关参数输入步骤，自动刮除步骤和分析步骤。 制备步骤包括制备多轴机床，激光位移计，自动刮除装置和计算机。 扫描步骤包括扫描工件。 平坦度参数输入步骤包括输入平坦度参数。 表面精加工步骤包括计算工件的被刮削范围并刮擦工件。 相关参数输入步骤包括在计算机中输入所需的PPI和POP，计算出HOP，DOS和油含量，以获得单次刮除过程的长度，宽度和深度。 自动刮削步骤包括刮擦工件以满足要求。 分析步骤包括检测工件的3D外观图。

公开(公告)号：US08039933B2

公开(公告)日：2011-10-18

申请号：US12840304

申请日：2010-07-21

申请人： Tung-Hsien Hsieh ,  Nan-Cheng Chen

发明人： Tung-Hsien Hsieh ,  Nan-Cheng Chen

IPC分类号： H01L23/495

CPC分类号： H01L23/3107 ,  H01L21/4832 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49586 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/4911 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19042 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A QFN semiconductor package includes a die attach pad; a semiconductor die mounted on the die attach pad; an inner terminal lead disposed adjacent to the die attach pad; a first wire bonding the inner terminal lead to the semiconductor die; an extended, outer terminal lead disposed along periphery of the QFN semiconductor package, wherein the extended, outer terminal lead is disposed beyond a maximum wire length which is provided for a specific minimum pad opening size on the semiconductor die; an intermediary terminal disposed between the inner terminal lead and the extended, outer terminal lead; a second wire bonding the intermediary terminal to the semiconductor die; and a third wire bonding the intermediary terminal to the extended, outer terminal lead.

摘要翻译： QFN半导体封装包括管芯附接垫; 安装在管芯附接垫上的半导体管芯; 设置在所述管芯附接垫附近的内部端子引线; 将内部端子引线接合到半导体管芯的第一引线; 延伸的外部端子引线，设置在所述QFN半导体封装的周围，其中所述延伸的外部端子引线设置在超过所述半导体管芯上的特定最小焊盘开口尺寸的最大焊丝长度之上; 设置在内端子引线和延伸外端子引线之间的中间端子; 将所述中间端子连接到所述半导体管芯的第二引线; 以及将中间终端连接到扩展的外部终端引线的第三引线。

公开(公告)号：US07884481B2

公开(公告)日：2011-02-08

申请号：US11946255

申请日：2007-11-28

申请人： Tung-Hsien Hsieh

发明人： Tung-Hsien Hsieh

IPC分类号： H01L23/22 ,  H01L23/24 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/49838 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/15311 ,  H05K1/114 ,  H05K3/242 ,  H05K2201/09709 ,  H05K2201/10734 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A semiconductor chip package is disclosed. The semiconductor chip package comprises a package substrate having a bottom surface. At least four adjacent ball pads are on the bottom surface, arranged in a first two-row array along a first direction and a second direction. At least four vias are drilled through the package substrate, arranged in a second two-row array, wherein each of the vias in a row of the second two-row array is offset by a first distance along the first direction and a second distance along the second direction from the connecting ball pads in a row of the first two-row array, and each of the vias in the other adjacent row of the second two-row array is offset by the first distance along an opposite direction to the first direction and the second distance along the second direction from the connecting ball pads in the other adjacent row of the first two-row array.

摘要翻译： 公开了半导体芯片封装。 半导体芯片封装包括具有底表面的封装衬底。 至少四个相邻的球垫位于底表面上，沿着第一方向和第二方向布置在第一两列阵列中。 至少四个通孔穿过封装衬底，布置在第二两列阵列中，其中第二两列阵列的一排中的每个通孔偏移沿着第一方向的第一距离和沿第一方向的第二距离 来自第一两列阵列的一行中的连接球焊盘的第二方向，并且第二两列阵列的另一相邻行中的每个通孔沿与第一方向相反的方向偏移第一距离 以及沿着第二方向从第一两列阵列的另一相邻行中的连接球焊盘的第二距离。