摘要:
A stack package usable in a three-dimensional (3D) system-in-package (SIP) includes a first semiconductor chip, a second semiconductor chip, and a supporter. The first semiconductor chip includes a through silicon via (TSV), and the second semiconductor chip is stacked on the first semiconductor chip and is electrically connected to the first semiconductor chip through the TSV of the first semiconductor chip. The supporter is attached onto the first semiconductor chip so as to be spaced apart from an edge of the second semiconductor chip.
摘要:
The image sensor package includes: an image sensor chip including an image sensing unit which is positioned in an upper central portion thereof and including a plurality of chip bonding pads formed around the image sensing; a transparent board including a lower surface on which a first line electrically connected to the chip bonding pads is formed and the transparent board being arranged with the image sensor chip so that the lower surface faces the image sensing unit; and a plurality of second lines connected to the first line and extending along sidewalls of the image sensor chip to be exposed under a lower surface of the image sensor chip.
摘要:
In one aspect, a bump electrode of a semiconductor device is formed by providing a substrate including a pad electrode, forming a seed layer over the pad electrode, and forming a mask layer over the seed layer which includes an opening aligned over the pad electrode. A barrier plating layer is electroplated within the opening over the seed layer, and a bump plating layer is electroplated over the barrier plating layer. The mask layer is removed, and the seed layer is etched using the bump plating layer as a mask.
摘要:
A wafer-level-chip-scale package and related method of fabrication are disclosed. The wafer-level-chip-scale package comprises a semiconductor substrate comprising an integrated circuit, a conductive ball disposed on the semiconductor substrate and electrically connected to the integrated circuit, and a protective portion formed from an insulating material and disposed on bottom and side surfaces of the semiconductor substrate.
摘要:
A wafer-level-chip-scale package and related method of fabrication are disclosed. The wafer-level-chip-scale package comprises a semiconductor substrate comprising an integrated circuit, a conductive ball disposed on the semiconductor substrate and electrically connected to the integrated circuit, and a protective portion formed from an insulating material and disposed on bottom and side surfaces of the semiconductor substrate.