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公开(公告)号：US06887758B2
公开(公告)日：2005-05-03
申请号：US10267153
申请日：2002-10-09
IPC分类号： H01L21/336 , H01L29/792 , H01L29/788
CPC分类号： H01L29/66825 , H01L29/66833 , H01L29/792
摘要： A semiconductor device (10) has a highly doped layer (26) having a first conductivity type uniformly implanted into the semiconductor substrate (20). An oxide-nitride-oxide structure (36, 38, 40) is formed over the semiconductor substrate (20). A halo region (46) having the first conductivity type is implanted at an angle in only a drain side of the oxide-nitride-oxide structure and extends under the oxide-nitride-oxide structure a predetermined distance from an edge of the oxide-nitride-oxide structure. A source (52) and drain (54) having a second conductivity type are implanted into the substrate (20). The resulting non-volatile memory cell provides a low natural threshold voltage to minimize threshold voltage drift during a read cycle. In addition, the use of the halo region (46) on the drain side allows a higher programming speed, and the highly doped layer (26) allows the use of a short channel device.
摘要翻译： 半导体器件（10）具有均匀地注入到半导体衬底（20）中的具有第一导电类型的高掺杂层（26）。 氧化物 - 氧化物 - 氧化物结构（36,38,40）形成在半导体衬底（20）上。 具有第一导电类型的卤素区域（46）以仅在氧化物 - 氧化物 - 氧化物结构的漏极侧的角度被注入，并且在氧化物 - 氮化物 - 氧化物结构之下延伸到氧化氮化物 - 氮化物的边缘的预定距离 氧化物结构。 具有第二导电类型的源极（52）和漏极（54）被注入衬底（20）中。 所得的非易失性存储单元提供低的自然阈值电压，以在读周期期间最小化阈值电压漂移。 此外，在漏极侧使用卤素区域（46）允许更高的编程速度，并且高掺杂层（26）允许使用短通道器件。
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2.发明授权公开(公告)号：US06713812B1
公开(公告)日：2004-03-30
申请号：US10267199
申请日：2002-10-09
IPC分类号： H01L29788
CPC分类号： H01L29/66825 , H01L27/11521 , H01L29/105 , H01L29/66833 , H01L29/792
摘要： A memory device (70) that uses a non-volatile storage element (38), such as nitride, has reduced read disturb, which is the problem of tending to increase the threshold voltage of a memory device (70) during a read. To reduce this effect, the memory device (70) uses a counterdoped channel (86) to lower the natural threshold voltage of the device (70). This counterdoping can even be of sufficient dosage to reverse the conductivity type of the channel (86) and causing a negative natural threshold voltage. This allows for a lower gate voltage during read to reduce the adverse effect of performing a read. An anti-punch through (ATP) region (74) below the channel (86) allows for the lightly doped or reversed conductivity type channel (86) to avoid short channel leakage. A halo implant (46) on the drain side (54, 53) assists in hot carrier injection (HCI) so that the HCI is effective even though the channel (86) is lightly doped or of reversed conductivity type.
摘要翻译： 使用诸如氮化物的非易失性存储元件（38）的存储器件（70）具有减少的读取干扰，这是读取期间倾向于增加存储器件（70）的阈值电压的问题。 为了减少这种影响，存储装置（70）使用反向通道（86）来降低装置（70）的自然阈值电压。 这种反渗透甚至可以具有足够的剂量来反转通道（86）的导电类型并导致负的自然阈值电压。 这在读取期间允许较低的栅极电压以减少执行读取的不利影响。 在沟道（86）下方的抗穿透（ATP）区域（74）允许轻掺杂或反向导电型通道（86）避免短沟道泄漏。 漏极侧（54,53）上的卤素注入（46）有助于热载流子注入（HCI），使得尽管通道（86）被轻掺杂或反向导电类型，HCI也是有效的。
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3.发明授权Non-volatile memory device with improved data retention and method therefor 有权具有改进的数据保留的非易失性存储器件及其方法公开(公告)号：US07432547B2
公开(公告)日：2008-10-07
申请号：US10779004
申请日：2004-02-13
IPC分类号： H01L21/8238
CPC分类号： H01L21/28202 , H01L29/42324 , H01L29/511 , H01L29/518 , H01L29/792
摘要： A semiconductor device (30) comprises an underlying insulating layer (34), an overlying insulating layer (42) and a charge storage layer (36) between the insulating layers (34, 42). The charge storage layer (36) and the overlying insulating layer (42) form an interface, where at least a majority of charge in the charge storage layer (36) is stored. This can be accomplished by forming a charge storage layer (36) with different materials such as silicon and silicon germanium layers or n-type and p-type material layers, in one embodiment. In another embodiment, the charge storage layer (36) comprises a dopant that is graded. By storing at least a majority of the charge at the interface between the charge storage layer (36) and the overlying insulating layer (42), the leakage of charge through the underlying insulating layer is decreased allowing for a thinner underlying insulating layer (34) to be used.
摘要翻译： 半导体器件（30）包括下层绝缘层（34），上覆绝缘层（42）和在绝缘层（34,42）之间的电荷存储层（36）。 电荷存储层（36）和上覆绝缘层（42）形成存储电荷存储层（36）中至少大部分电荷的界面。 这可以通过在一个实施例中通过形成具有不同材料的电荷存储层（36）来实现，例如硅和硅锗层或n型和p型材料层。 在另一个实施例中，电荷存储层（36）包括分级的掺杂剂。 通过在电荷存储层（36）和上覆绝缘层（42）之间的界面处存储至少大部分电荷，通过下面的绝缘层的电荷泄漏减小，允许更薄的下层绝缘层（34） 要使用的。
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4.发明授权Method of fabricating a storage device including decontinuous storage elements within and between trenches 有权制造包括槽内和沟槽之间的不连续存储元件的存储装置的方法公开(公告)号：US07592224B2
公开(公告)日：2009-09-22
申请号：US11393287
申请日：2006-03-30
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , B82Y10/00 , G11C16/0458 , G11C2216/06 , H01L27/11521 , H01L29/42328 , H01L29/42332 , H01L29/42336 , H01L29/66825
摘要： A semiconductor storage cell includes a first source/drain region underlying a first trench defined in a semiconductor layer. A second source/drain region underlies a second trench in the semiconductor layer. A first select gate in the first trench and a second select gate in the second trench are lined by a select gate dielectric. A charge storage stack overlies the select gates and a control gate overlies the stack. The DSEs may comprise discreet accumulations of polysilicon. An upper surface of the first and second select gates is lower than an upper surface of the first and second trenches. The control gate may be a continuous control gate traversing and running perpendicular to the select gates. The cell may include contacts to the semiconductor layer. The control gate may include a first control gate overlying the first select gate and a second control gate overlying the second select gate.
摘要翻译： 半导体存储单元包括在半导体层中限定的第一沟槽下面的第一源极/漏极区域。 第二源极/漏极区域位于半导体层中的第二沟槽的下方。 第一沟槽中的第一选择栅极和第二沟槽中的第二选择栅极由选择栅极电介质排列。 电荷存储堆叠覆盖选择栅极，并且控制栅极覆盖堆叠。 DSE可以包括多晶硅的谨慎积累。 第一和第二选择栅极的上表面比第一和第二沟槽的上表面低。 控制栅极可以是垂直于选择栅极横穿并行进的连续控制栅极。 电池可以包括到半导体层的触点。 控制栅极可以包括覆盖第一选择栅极的第一控制栅极和覆盖第二选择栅极的第二控制栅极。
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公开(公告)号：US07619270B2
公开(公告)日：2009-11-17
申请号：US11188591
申请日：2005-07-25
IPC分类号： H01L29/72
CPC分类号： H01L29/7881 , B82Y10/00 , G11C16/0433 , G11C16/0458 , G11C16/0475 , G11C16/0491 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11556 , H01L27/11568 , H01L29/42332 , H01L29/42336 , H01L29/42348 , H01L29/42352 , H01L29/66825 , H01L29/66833 , H01L29/792 , H01L29/7926
摘要： An electronic device can include discontinuous storage elements that lie within a trench. The electronic device can include a substrate including a trench that includes a wall and a bottom and extends from a primary surface of the substrate. The electronic device can also include discontinuous storage elements, wherein a portion of the discontinuous storage elements lies at least within the trench. The electronic device can further include a first gate electrode, wherein at least a part of the portion of the discontinuous storage elements lies between the first gate electrode and the wall of the trench. The electronic device can still further include a second gate electrode overlying the first gate electrode and the primary surface of the substrate.
摘要翻译： 电子设备可以包括位于沟槽内的不连续存储元件。 电子器件可以包括包括沟槽的衬底，其包括壁和底部并且从衬底的主表面延伸。 电子设备还可以包括不连续的存储元件，其中不连续存储元件的一部分至少位于沟槽内。 电子器件还可以包括第一栅极电极，其中不连续存储元件的部分的至少一部分位于第一栅电极和沟槽的壁之间。 电子器件还可以包括覆盖在第一栅电极和衬底的主表面上的第二栅电极。
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公开(公告)号：US20070020857A1
公开(公告)日：2007-01-25
申请号：US11188939
申请日：2005-07-25
IPC分类号： H01L21/336
CPC分类号： B82Y10/00 , H01L21/7624 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11556 , H01L29/42328 , H01L29/42332 , H01L29/42336 , H01L29/42344 , H01L29/42348 , H01L29/42352 , Y10S977/707
摘要： A process for forming an electronic device can include forming a first trench within a substrate, wherein the trench includes a wall and a bottom and extends from a primary surface of the substrate. The process can also include forming discontinuous storage elements and forming a first gate electrode within the trench such that, a first discontinuous storage element of the discontinuous storage elements lies between the first gate electrode and the wall of the trench. The process can further include removing the discontinuous storage elements that overlie the primary surface of the substrate. The process can still further include forming a second gate electrode that overlies the first gate electrode and the primary surface of the substrate.
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公开(公告)号：US07206214B2
公开(公告)日：2007-04-17
申请号：US11197814
申请日：2005-08-05
IPC分类号： G11C17/00
CPC分类号： G11C17/16 , G11C17/18 , H01L27/112
摘要： A one time programmable (OTP) memory has two-bit cells for increasing density. Each cell has two select transistors and a programmable transistor in series between the two select transistors. The programmable transistor has two independent storage locations. One is between the gate and a first source/drain region and the second is between the gate and a second source/drain region. The storage locations are portions of the gate dielectric where the sources or drains overlap the gate and are independently programmed by selectively passing a programming current through them. The programming current is of sufficient magnitude and duration to permanently reduce the impedance by more than three orders of magnitude of the storage locations to be programmed. The programming current is limited in magnitude to avoid damage to other circuit elements and is preferably induced at least in part by applying a negative voltage to the gate of the programming transistor.
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公开(公告)号：US06724032B2
公开(公告)日：2004-04-20
申请号：US10202697
申请日：2002-07-25
IPC分类号： H01L27108
CPC分类号： H01L27/11568 , H01L27/1052 , H01L27/115 , H01L27/11521 , H01L29/7782 , H01L29/7923
摘要： A non-volatile multiple bit memory (10, 50) has electrically isolated storage elements (17, 21, 78, 80) that overlie a channel region having a central area (24, 94) with high impurity concentration. A planar gate (30, 84) overlies the storage elements. The high impurity concentration may be formed by a centrally located region (24) or by two peripheral regions (70, 72) having lower impurity concentration than the central portion of the channel. During a read or program operation, the channel area of high impurity concentration effectively controls a channel depletion region to enhance reading or programming of stored data bits. During a hot carrier program operation, the channel area of high impurity concentration enhances the programming efficiency by decreasing leakage currents in a memory array.
摘要翻译： 非易失性多位存储器（10,50）具有覆盖在具有高杂质浓度的中心区域（24,94）的沟道区域上的电隔离存储元件（17,21,78,80）。 平面栅极（30,84）覆盖存储元件。 高杂质浓度可以由中心定位的区域（24）或具有比通道中心部分低的杂质浓度的两个外围区域（70,72）形成。 在读取或编程操作期间，高杂质浓度的沟道区域有效地控制沟道耗尽区域以增强对存储的数据位的读取或编程。 在热载波编程操作期间，高杂质浓度的沟道区域通过减少存储器阵列中的漏电流来提高编程效率。
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9.发明授权Programming and erasing structure for a floating gate memory cell and method of making 有权浮动存储单元的编程和擦除结构及其制作方法公开(公告)号：US07745870B2
公开(公告)日：2010-06-29
申请号：US11626681
申请日：2007-01-24
IPC分类号： H01L29/76
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42324
摘要： A floating gate memory cell has a floating gate in which there are two floating gate layers. The top layer is etched to provide a contour in the top layer while leaving the lower layer unchanged. The control gate follows the contour of the floating gate to increase capacitance therebetween. The two layers of the floating gate can be polysilicon separated by a very thin etch stop layer. This etch stop layer is thick enough to provide an etch stop during a polysilicon etch but preferably thin enough to be electrically transparent. Electrons are able to easily move between the two layers. Thus the etch of the top layer does not extend into the lower layer but the first and second layer have the electrical effect for the purposes of a floating gate of being a continuous conductive layer.
摘要翻译： 浮动栅极存储单元具有浮置栅极，其中存在两个浮置栅极层。 蚀刻顶层以在顶层中提供轮廓，同时保持下层不变。 控制栅极跟随浮动栅极的轮廓以增加它们之间的电容。 浮置栅极的两层可以是由非常薄的蚀刻停止层分离的多晶硅。 该蚀刻停止层足够厚以在多晶硅蚀刻期间提供蚀刻停止，但优选足够薄以使其具有电透明性。 电子能够容易地在两层之间移动。 因此，顶层的蚀刻不延伸到下层，但是为了作为连续导电层的浮动栅极的目的，第一和第二层具有电效应。
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公开(公告)号：US20090170262A1
公开(公告)日：2009-07-02
申请号：US12397905
申请日：2009-03-04
IPC分类号： H01L21/8239
CPC分类号： H01L27/115 , H01L27/11521 , Y10S438/926 , Y10S438/962
摘要： A virtual ground memory array (VGA) is formed by a storage layer over a substrate with a conductive layer over the storage layer. The conductive layer is opened according to a patterned photoresist layer. The openings are implanted to form source/drain lines in the substrate, then filled with a layer of dielectric material. Chemical mechanical polishing (CMP) is then performed until the top of the conductive layer is exposed. This leaves dielectric spacers over the source/drain lines and conductive material between the dielectric spacers. Word lines are then formed over the conductive material and the dielectric spacers. As an alternative, instead of using a conductive layer, a sacrificial layer is used that is removed after the CMP step. After removing the sacrificial portions, the word lines are formed. In both cases, dielectric spacers reduce gate/drain capacitance and the distance from substrate to gate is held constant across the channel.
摘要翻译： 虚拟接地存储器阵列（VGA）由存储层上的存储层形成在衬底上，在存储层上方具有导电层。 根据图案化的光致抗蚀剂层打开导电层。 注入开口以在衬底中形成源极/漏极线，然后填充一层电介质材料。 然后进行化学机械抛光（CMP），直到暴露导电层的顶部。 这使得源极/漏极线之间的电介质间隔物和电介质间隔物之间的导电材料留下。 然后在导电材料和电介质间隔物上形成字线。 作为替代，代替使用导电层，使用在CMP步骤之后去除的牺牲层。 在去除牺牲部分之后，形成字线。 在这两种情况下，介质间隔物减少了栅极/漏极电容，并且从衬底到栅极的距离在通道上保持恒定。
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