公开(公告)号：US6140234A

公开(公告)日：2000-10-31

申请号：US9824

申请日：1998-01-20

Applicant: Cyprian Emeka Uzoh ,  Stephen Edward Greco

Inventor： Cyprian Emeka Uzoh ,  Stephen Edward Greco

IPC: C25D5/02 ,  C23C18/31 ,  C25D7/12 ,  H01L21/288 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/44

CPC classification number: H01L21/76843 ,  H01L21/2885 ,  H01L21/76807 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76879 ,  H01L2924/0002

Abstract: Recesses in a semiconductor structure are selectively plated by providing electrical insulating layer over the semiconductor substrate and in the recesses followed by forming a conductive barrier over the insulating layer; providing a plating seed layer over the barrier layer; depositing and patterning a photoresist layer over the plating seed layer; planarizing the insulated horizontal portions by removing the horizontal portions of the seed layer between the recesses; removing the photoresist remaining in the recesses; and then electroplating the patterned seed layer with a conductive metal using the barrier layer to carry the current during the electroplating to thereby only plate on the seed layer.In an alternative process, a barrier film is deposited over recesses in an insulator. Then, relatively thick resists are lithographically defined on the field regions, on top of the barrier film over the recesses. A plating base or seedlayer is deposited, so as to be continuous on the horizontal regions of the recesses in the insulator, but discontinuous on their surround wall. The recesses are then plated using the barrier film without seedlayers at the periphery of the substrate wafers for electrical contact. After electroplating, the resist is removed by lift-off process and exposed barrier film is etched by RIE method or by CMP.Also provided is a semiconductor structure obtained by the above processes.

Abstract translation: 通过在半导体衬底上和凹槽内提供电绝缘层，然后在绝缘层上形成导电阻挡层来选择性地镀覆半导体结构中的凹陷; 在所述阻挡层上提供电镀种子层; 在所述电镀种子层上沉积和图案化光致抗蚀剂层; 通过去除凹槽之间的晶种层的水平部分来平坦化绝缘水平部分; 去除残留在凹槽中的光致抗蚀剂; 然后使用阻挡层用导电金属电镀图案化种子层，以在电镀期间承载电流，从而仅在种子层上铺板。 在替代方法中，阻挡膜沉积在绝缘体中的凹部上。 然后，相对厚的抗蚀剂被光刻地限定在场区域上，在阻挡膜上方的凹部上。 沉积电镀基底或种子层，以便在绝缘体中的凹部的水平区域上连续地连续，但是在它们的环绕壁上是不连续的。 然后，在基板晶片的周边使用阻挡膜将凹槽进行电镀，而不需要用于电接触的晶片的边缘。 电镀后，通过剥离工艺除去抗蚀剂，并通过RIE法或CMP蚀刻暴露的阻挡膜。 还提供了通过上述方法获得的半导体结构。

公开(公告)号：US07456501B1

公开(公告)日：2008-11-25

申请号：US09611955

申请日：2000-07-06

Applicant: Cyprian Emeka Uzoh ,  Stephen Edward Greco

Inventor： Cyprian Emeka Uzoh ,  Stephen Edward Greco

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L21/76843 ,  H01L21/2885 ,  H01L21/76807 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76879 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure includes a semiconductor substrate, a recess located in at least one major surface of the substrate, an electrical insulating layer located over the at least one major surface and in the recess, a conductive barrier located over the insulating layer and in the recess and over the at least one major surface, a plating seed layer located over the conductive barrier within the recess only, and a conductive metal in the recess only.

Abstract translation: 半导体结构包括半导体衬底，位于衬底的至少一个主表面中的凹部，位于至少一个主表面和凹部中的电绝缘层，位于绝缘层上方和凹部中的导电阻挡层 并且在所述至少一个主表面上，仅位于所述凹部内的导电阻挡层上方的电镀种子层，以及仅在所述凹部中的导电金属。

公开(公告)号：US07488679B2

公开(公告)日：2009-02-10

申请号：US11461137

申请日：2006-07-31

Applicant: Theodorus Eduardus Standaert ,  Pegeen M. Davis ,  John Anthony Fitzsimmons ,  Stephen Edward Greco ,  Tze-Man Ko ,  Naftali Eliahu Lustig ,  Lee Matthew Nicholson ,  Sujatha Sankaran

Inventor： Theodorus Eduardus Standaert ,  Pegeen M. Davis ,  John Anthony Fitzsimmons ,  Stephen Edward Greco ,  Tze-Man Ko ,  Naftali Eliahu Lustig ,  Lee Matthew Nicholson ,  Sujatha Sankaran

IPC: H01L21/4763 ,  H01L23/48

CPC classification number: H01L21/76808 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76846 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming an interconnect structure in an inter-layer dielectric (ILD) material, the method include the steps of creating one or more via openings in the ILD material; forming a first liner covering at least one of the one or more via openings; creating one or more trench openings on top of at least one of the one or more via openings covered by the first liner; and forming a second liner covering the trenching openings and at least part of the first liner. An interconnect structure formed by the method is also provided.

Abstract translation: 一种在层间电介质（ILD）材料中形成互连结构的方法，所述方法包括以下步骤：在ILD材料中形成一个或多个通路孔; 形成覆盖所述一个或多个通孔开口中的至少一个的第一衬垫; 在由所述第一衬垫覆盖的所述一个或多个通孔中的至少一个的顶部上形成一个或多个沟槽开口; 以及形成覆盖所述下料开口和所述第一衬里的至少一部分的第二衬里。 还提供了通过该方法形成的互连结构。

公开(公告)号：US07300825B2

公开(公告)日：2007-11-27

申请号：US10835953

申请日：2004-04-30

Applicant: Nancy Anne Greco ,  Stephen Edward Greco ,  Erik L. Hedberg

Inventor： Nancy Anne Greco ,  Stephen Edward Greco ,  Erik L. Hedberg

IPC: H01L21/00

CPC classification number: H01L21/76895 ,  H01L24/05 ,  H01L2224/05624 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/01029 ,  H01L2924/00

Abstract: Custom connections between pairs of copper wires in a last damascene wiring level are effected by creating openings in an overlying insulating layer which span a distance between portions of the two wires, then filling the openings with aluminum. The openings can be created (or completed) by a second, maskless UV laser exposure of positive photoresist which is used for patterning the insulating layer. If an opening is not created, an aluminum connecting shape overlying the insulating layer will not effect a connection between the two wires. Similar results can be achieved by laser exposure of a resist used to pattern the aluminum layer, thereby causing breaks in connecting shape when it is desired not to have a connection.

Abstract translation: 在最后一个镶嵌布线层次中的铜线对之间的定制连接是通过在覆盖的绝缘层中形成开口，跨越两条线的部分之间的距离，然后用铝填充开口。 可以通过用于图案化绝缘层的正性光致抗蚀剂的第二次无掩模UV激光曝光来创建（或完成）开口。 如果不产生开口，则覆盖绝缘层的铝连接形状将不会影响两条电线之间的连接。 通过用于图案化铝层的抗蚀剂的激光曝光可以实现类似的结果，从而当期望不连接时，导致连接形状的断裂。

公开(公告)号：US06573606B2

公开(公告)日：2003-06-03

申请号：US09881444

申请日：2001-06-14

Applicant: Carlos Juan Sambucetti ,  Xiaomeng Chen ,  Soon-Cheon Seo ,  Birenda Nath Agarwala ,  Chao-Kun Hu ,  Naftali Eliahu Lustig ,  Stephen Edward Greco

Inventor： Carlos Juan Sambucetti ,  Xiaomeng Chen ,  Soon-Cheon Seo ,  Birenda Nath Agarwala ,  Chao-Kun Hu ,  Naftali Eliahu Lustig ,  Stephen Edward Greco

IPC: H01L2144

CPC classification number: H01L23/53238 ,  H01L21/76849 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In the invention an electrically isolated copper interconnect structural interface is provided involving a single, about 50-300 A thick, alloy capping layer, that controls diffusion and electromigration of the interconnection components and reduces the overall effective dielectric constant of the interconnect; the capping layer being surrounded by a material referred to in the art as hard mask material that can provide a resist for subsequent reactive ion etching operations, and there is also provided the interdependent process steps involving electroless deposition in the fabrication of the structural interface. The single layer alloy metal barrier in the invention is an alloy of the general type A—X—Y, where A is a metal taken from the group of cobalt (Co) and nickel (Ni), X is a member taken from the group of tungsten (W), tin (Sn), and silicon (Si), and Y is a member taken from the group of phosphorous (P) and boron (B); having a thickness in the range of 50 to 300 Angstroms.

Abstract translation: 在本发明中，提供了电隔离的铜互连结构界面，其涉及单个约50-300A厚的合金覆盖层，其控制互连部件的扩散和电迁移并且降低互连的整体有效介电常数; 封盖层被本领域中称为材料所包围的材料包围，其可以为随后的反应离子蚀刻操作提供抗蚀剂，并且还提供了在结构界面的制造中涉及无电沉积的相互依赖的工艺步骤。 本发明中的单层合金金属阻挡层是一般型AXY的合金，其中A是从钴（Co）和镍（Ni）中取出的金属，X是取自钨（W ），锡（Sn）和硅（Si），Y是从磷（P）和硼（B）取代的成员; 厚度在50至300埃的范围内。

公开(公告)号：US06831364B2

公开(公告)日：2004-12-14

申请号：US10210173

申请日：2002-08-01

Applicant: Timothy Joseph Dalton ,  Stephen Edward Greco ,  Jeffrey Curtis Hedrick ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Kenneth Parker Rodbell ,  Robert Rosenberg

Inventor： Timothy Joseph Dalton ,  Stephen Edward Greco ,  Jeffrey Curtis Hedrick ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Kenneth Parker Rodbell ,  Robert Rosenberg

IPC: H01L2352

CPC classification number: H01L21/02126 ,  H01L21/02203 ,  H01L21/02362 ,  H01L21/31695 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76828 ,  H01L23/5329 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a porous dielectric material layer in an electronic structure and the structure formed are disclosed. In the method, a porous dielectric layer in a semiconductor device can be formed by first forming a non-porous dielectric layer, then partially curing, patterning by reactive ion etching, and final curing the non-porous dielectric layer at a higher temperature than the partial curing temperature to transform the non-porous dielectric material into a porous dielectric material, thus forming a dielectric material that has a low dielectric constant, i.e. smaller than 2.6. The non-porous dielectric material may be formed by embedding a thermally stable dielectric material such as methyl silsesquioxane, hydrogen silsesquioxane, benzocyclobutene or aromatic thermoset polymers with a second phase polymeric material therein such that, at the higher curing temperature, the second phase polymeric material substantially volatilizes to leave voids behind forming a void-filled dielectric material.

Abstract translation: 公开了一种在电子结构中形成多孔介电材料层的方法和形成的结构。 在该方法中，半导体器件中的多孔电介质层可以通过首先形成无孔介电层，然后通过反应离子蚀刻进行部分固化，图案化，并且在比无孔介电层更高的温度下最终固化无孔介电层 部分固化温度以将无孔电介质材料转变为多孔电介质材料，从而形成具有低介电常数（即小于2.6）的电介质材料。 无孔介电材料可以通过将热稳定的介电材料如甲基倍半硅氧烷，氢倍半硅氧烷，苯并环丁烯或芳族热固性聚合物与其中的第二相聚合物材料嵌入而形成，使得在较高固化温度下，第二相聚合物材料 基本上挥发以在形成空隙填充的电介质材料之后留下空隙。

公开(公告)号：US06451712B1

公开(公告)日：2002-09-17

申请号：US09739935

申请日：2000-12-18

Applicant: Timothy Joseph Dalton ,  Stephen Edward Greco ,  Jeffrey Curtis Hedrick ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Kenneth Parker Rodbell ,  Robert Rosenberg

Inventor： Timothy Joseph Dalton ,  Stephen Edward Greco ,  Jeffrey Curtis Hedrick ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Kenneth Parker Rodbell ,  Robert Rosenberg

IPC: H01L2131

CPC classification number: H01L21/02126 ,  H01L21/02203 ,  H01L21/02362 ,  H01L21/31695 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76828 ,  H01L23/5329 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a porous dielectric material layer in an electronic structure and the structure formed are disclosed. In the method, a porous dielectric layer in a semiconductor device can be formed by first forming a non-porous dielectric layer, then partially curing, patterning by reactive ion etching, and final curing the non-porous dielectric layer at a higher temperature than the partial curing temperature to transform the non-porous dielectric material into a porous dielectric material, thus achieving a dielectric material that has significantly improved dielectric constant, i.e. smaller than 2.6. The non-porous dielectric material may be formed by embedding a thermally stable dielectric material such as methyl silsesquioxane, hydrogen silsesquioxane, benzocyclobutene or aromatic thermoset polymers with a second phase polymeric material therein such that, at the higher curing temperature, the second phase polymeric material substantially volatilizes to leave voids behind forming a void-filled dielectric material.

Abstract translation: 公开了一种在电子结构中形成多孔介电材料层的方法和形成的结构。 在该方法中，半导体器件中的多孔电介质层可以通过首先形成无孔介电层，然后通过反应离子蚀刻进行部分固化，图案化，并且在比无孔介电层更高的温度下最终固化无孔介电层 部分固化温度以将无孔电介质材料转化为多孔电介质材料，从而获得具有显着改善介电常数（即小于2.6）的电介质材料。 无孔介电材料可以通过将热稳定的介电材料如甲基倍半硅氧烷，氢倍半硅氧烷，苯并环丁烯或芳族热固性聚合物与其中的第二相聚合物材料嵌入而形成，使得在较高的固化温度下，第二相聚合物材料 基本上挥发以在形成空隙填充的电介质材料之后留下空隙。

公开(公告)号：US20080026568A1

公开(公告)日：2008-01-31

申请号：US11461137

申请日：2006-07-31

Applicant: Theodorus Eduardus Standaert ,  Pegeen M. Davis ,  John Anthony Fitzsimmons ,  Stephen Edward Greco ,  Tze-Man Ko ,  Naftali Eliahu Lustig ,  Lee Matthew Nicholson ,  Sujatha Sankaran

Inventor： Theodorus Eduardus Standaert ,  Pegeen M. Davis ,  John Anthony Fitzsimmons ,  Stephen Edward Greco ,  Tze-Man Ko ,  Naftali Eliahu Lustig ,  Lee Matthew Nicholson ,  Sujatha Sankaran

IPC: H01L21/4763

CPC classification number: H01L21/76808 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76846 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming an interconnect structure in an inter-layer dielectric (ILD) material, the method include the steps of creating one or more via openings in the ILD material; forming a first liner covering at least one of the one or more via openings; creating one or more trench openings on top of at least one of the one or more via openings covered by the first liner; and forming a second liner covering the trenching openings and at least part of the first liner. An interconnect structure formed by the method is also provided.

Abstract translation: 一种在层间电介质（ILD）材料中形成互连结构的方法，所述方法包括以下步骤：在ILD材料中形成一个或多个通路孔; 形成覆盖所述一个或多个通孔开口中的至少一个的第一衬垫; 在由所述第一衬垫覆盖的所述一个或多个通孔中的至少一个的顶部上形成一个或多个沟槽开口; 以及形成覆盖所述下料开口和所述第一衬里的至少一部分的第二衬里。 还提供了通过该方法形成的互连结构。

公开(公告)号：US07253098B2

公开(公告)日：2007-08-07

申请号：US10711145

申请日：2004-08-27

Applicant: Shyng-Tsong T. Chen ,  Kaushik Arun Kumar ,  Stephen Edward Greco ,  Shom Ponoth ,  Terry Allen Spooner ,  David L. Rath ,  Wei-Tsu Tseng

Inventor： Shyng-Tsong T. Chen ,  Kaushik Arun Kumar ,  Stephen Edward Greco ,  Shom Ponoth ,  Terry Allen Spooner ,  David L. Rath ,  Wei-Tsu Tseng

IPC: H01L21/4763

CPC classification number: H01L21/7684 ,  H01L21/3212 ,  H01L21/76832 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A chemical mechanical polishing (CMP) step is used to remove excess conductive material (e.g., Cu) overlying a low-k or ultralow-k interlevel dielectric layer (ILD) layer having trenches filled with conductive material, for a damascene interconnect structure. A reactive ion etch (RIE) or a Gas Cluster Ion Beam (GCIB) process is used to remove a portion of a liner which is atop a hard mask. A wet etch step is used to remove an oxide portion of the hard mask overlying the ILD, followed by a final touch-up Cu CMP (CMP) step which chops the protruding Cu patterns off and lands on the SiCOH hard mask. In this manner, processes used to remove excess conductive material substantially do not affect the portion of the hard mask overlying the interlevel dielectric layer.

Abstract translation: 化学机械抛光（CMP）步骤用于去除覆盖在具有填充有导电材料的沟槽的低k或超低k层间介质层（ILD）层上的过剩导电材料（例如Cu），用于镶嵌互连结构。 使用反应离子蚀刻（RIE）或气体簇离子束（GCIB）方法去除位于硬掩模顶部的衬垫的一部分。 使用湿蚀刻步骤去除覆盖在ILD上的硬掩模的氧化物部分，随后是最后的上覆Cu CMP（CMP）步骤，其将突出的Cu图案切掉并落在SiCOH硬掩模上。 以这种方式，用于去除过量的导电材料的工艺基本上不影响覆盖层间电介质层的硬掩模的部分。

公开(公告)号：US06121129A

公开(公告)日：2000-09-19

申请号：US784158

申请日：1997-01-15

Applicant: Nancy Anne Greco ,  Stephen Edward Greco ,  Tina Jane Wagner

Inventor： Nancy Anne Greco ,  Stephen Edward Greco ,  Tina Jane Wagner

IPC: H01L21/28 ,  H01L21/768 ,  H01L21/4763

CPC classification number: H01L21/768 ,  H01L21/76877

Abstract: A method of forming a semiconductor structure having features of differing sizes, includes forming a first layer on a semiconductor substrate; patterning only a first plurality of features of a first feature size on the first layer; removing portions of the first layer, the portions corresponding to the first plurality of features, filling the first plurality of openings; forming a second layer, the second layer overlying the first layer and the filled openings; patterning a second plurality of features of a second feature size on the second layer; removing portions of the first layer and second layer, the portions corresponding to the second plurality of features, the second plurality of openings extending through the first and second layers, and filling the second plurality openings.

Abstract translation: 一种形成具有不同尺寸特征的半导体结构的方法，包括在半导体衬底上形成第一层; 仅在第一层上构图第一特征尺寸的第一多个特征; 去除第一层的部分，对应于第一多个特征的部分，填充第一多个开口; 形成第二层，所述第二层覆盖所述第一层和所述填充的开口; 在第二层上构图第二特征尺寸的第二多个特征; 去除第一层和第二层的部分，对应于第二多个特征的部分，第二多个开口延伸穿过第一和第二层，并填充第二多个开口。