公开(公告)号：US10453956B2

公开(公告)日：2019-10-22

申请号：US16436939

申请日：2019-06-11

Applicant: DELTA ELECTRONICS, INC.

Inventor： Chao-Feng Cai ,  Jian-Hong Zeng ,  Zeng Li ,  Xiao-Ni Xin

IPC: H01L29/78 ,  H01L23/50 ,  H01L23/00 ,  H01L29/10 ,  H01L29/40 ,  H01L29/417

Abstract: A semiconductor packaging structure includes a chip, a first pin, a second pin, and a third pin. The chip includes a first surface, a second surface, a first power switch, and a second switch, and both the first power switch and the second switch include a first terminal and a second terminal. The second surface of the chip is opposite to the first surface of the chip. The first pin does not contact to the second pin. The first terminal of the first power switch of the chip is coupled to the first pin, and the second terminal of the first power switch of the chip is coupled to the third pin. The first terminal of the second power switch of the chip is coupled to the third pin, and the second terminal of the second power switch of the chip is coupled to the second pin.

公开(公告)号：US10096562B2

公开(公告)日：2018-10-09

申请号：US15209777

申请日：2016-07-14

Applicant: DELTA ELECTRONICS, INC.

Inventor： Le Liang ,  Kai Lu ,  Zhen-Qing Zhao ,  Zeng Li

IPC: H01L29/15 ,  H01L23/00 ,  H01L23/498 ,  H01L23/31 ,  H01L25/16 ,  H01L25/18

Abstract: A power module package includes a single-layered circuit board, a first electronic component, and a second electronic component. The single-layered circuit board includes an insulating substrate and a conductive layer thereon. A bottom surface of the conductive layer touches a top surface of the insulating substrate. The insulating substrate has plural first openings to allow the conductive layer to be exposed from the bottom surface of the insulating substrate. The first electronic component is disposed on a top surface of the conductive layer. The second electronic component is disposed on the bottom surface of the insulating substrate and received in the first openings. The second electronic component is connected to the conductive layer via the first openings. At least one of the first electronic component and the second electronic component is a bare die.

公开(公告)号：US09559606B2

公开(公告)日：2017-01-31

申请号：US14962074

申请日：2015-12-08

Applicant: DELTA ELECTRONICS, INC.

Inventor： Juncheng Lu ,  Zeng Li

IPC: H02M7/00 ,  H02M7/538 ,  H02M7/797

CPC classification number: H02M7/003 ,  H02M7/538 ,  H02M7/797

Abstract: A layout of a switching power converter, wherein the switching power converter includes: a capacitor unit receiving or outputting DC voltage; six power transistor units transforming the DC voltage to the AC voltage or the AC voltage to the DC voltage; and a carrier board with the capacitor unit and the six power transistor units on. The layout of the switching power converter includes a first commutation loop and a second commutation loop, in which the six power transistor units are arranged on the same surface of the carrier board. In order to ensure the first commutation loop and the second commutation loop as short as possible, the fifth power transistor unit is located at a middle position of the carrier board, surrounded by the other five power transistor units as closely as possible.

Abstract translation: 一种开关电源转换器的布局，其中开关电源转换器包括：接收或输出直流电压的电容器单元; 六个功率晶体管单元将DC电压转换为AC电压或AC电压至DC电压; 和带有电容器单元和六个功率晶体管单元的载板。 开关功率转换器的布局包括第一换向环和第二换向环，其中六个功率晶体管单元布置在载板的同一表面上。 为了确保第一换向回路和第二换向回路尽可能短，第五功率晶体管单元位于载板的中间位置，由其它五个功率晶体管单元尽可能靠近地围绕。

公开(公告)号：US10347758B2

公开(公告)日：2019-07-09

申请号：US15647278

申请日：2017-07-12

Applicant: DELTA ELECTRONICS, INC.

Inventor： Chao-Feng Cai ,  Jian-Hong Zeng ,  Zeng Li

IPC: H01L29/417 ,  H01L29/78 ,  H01L23/50 ,  H01L23/00 ,  H01L29/40 ,  H01L29/10

Abstract: A semiconductor packaging structure includes a chip, a first pin, a second pin, and a third pin. The chip includes a first surface, a second surface, a first power switch, and a second switch, and both the first power switch and the second switch include a first terminal and a second terminal. The second surface of the chip is opposite to the first surface of the chip. The first pin does not contact to the second pin. The first terminal of the first power switch of the chip is coupled to the first pin, and the second terminal of the first power switch of the chip is coupled to the third pin. The first terminal of the second power switch of the chip is coupled to the third pin, and the second terminal of the second power switch of the chip is coupled to the second pin.

公开(公告)号：US10020731B2

公开(公告)日：2018-07-10

申请号：US14959071

申请日：2015-12-04

Applicant: DELTA ELECTRONICS, INC.

Inventor： Zeng Li ,  Chaofeng Cai

IPC: H01H19/64 ,  H02M3/158 ,  H02M1/00

CPC classification number: H02M3/158 ,  H02M2001/0054 ,  Y02B70/1491

Abstract: A power switch circuit includes at least one switch unit including at least one first switch and one second switch which are connected in parallel. A turning-on loss of the first switch is smaller than a turning-on loss of the second switch, a turning-off loss of the first switch is larger than a turning-off loss of the second switch; during one controlling period of the switch unit, when the switch unit is controlled to be turned on, a moment when the first switch is turned on is controlled to be earlier than a moment when the second switch is turned on; and when the switch unit is controlled to be turned off, a moment when the first switch is turned off is controlled to be earlier than a moment when the second switch is turned off.

公开(公告)号：US09887183B2

公开(公告)日：2018-02-06

申请号：US15151730

申请日：2016-05-11

Applicant: DELTA ELECTRONICS, INC.

Inventor： Tao Wang ,  Zhenqing Zhao ,  Zeng Li ,  Kai Lu

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/053 ,  H01L23/31 ,  H01L23/498 ,  H01L25/07 ,  H01L23/24

CPC classification number: H01L25/162 ,  H01L23/053 ,  H01L23/24 ,  H01L23/3735 ,  H01L23/49811 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5385 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/0603 ,  H01L2224/29139 ,  H01L2224/29147 ,  H01L2224/32225 ,  H01L2224/37147 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/4903 ,  H01L2224/73265 ,  H01L2224/85205 ,  H01L2224/85801 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/05032 ,  H01L2924/05042 ,  H01L2924/0532 ,  H01L2924/05432 ,  H01L2924/12035 ,  H01L2924/1205 ,  H01L2924/1207 ,  H01L2924/13023 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1426 ,  H01L2924/15724 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/15763 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2224/05599

Abstract: The present disclosure provides a power module with the integration of a control circuit at least, including: a power substrate; a power device mounted on the power substrate; and at least one control substrate which supports the control circuit, is electrically connected with the power substrate and disposed at an angle of inclination on a surface of the power substrate on which the power device is mounted; wherein the angle of inclination is greater than or equal to 45 degrees and smaller than or equal to 135 degrees. In the power module provided by the present disclosure, only the power substrate as well as the connections between the control substrate and the power substrate occupies the footprint area of the power module, and thus the horizontal footprint area of the power module is effectively reduced and thereby the power density of the power module is increased.

公开(公告)号：US09973185B2

公开(公告)日：2018-05-15

申请号：US14813140

申请日：2015-07-30

Applicant: DELTA ELECTRONICS, INC.

Inventor： Zeng Li ,  Chao-Feng Cai

IPC: H02H3/28 ,  H03K17/687 ,  H03K17/082 ,  H03K17/567

CPC classification number: H03K17/0828 ,  H03K17/567 ,  H03K17/6871 ,  H03K2017/6875

Abstract: A cascode switch device includes a cascode circuit, which includes a first switch and a second switch, and a protection circuit. The protection circuit is coupled between the first switch and the second switch. A first leakage current passing through the protection circuit is greater than or equal to a difference between a second leakage current and a third leakage current, and is smaller than an upper limit value of a leakage current of the cascode circuit. An upper limit value of a withstanding voltage is present between the first terminal and the control terminal of the first switch. When the first switch operates at the upper limit value of the withstanding voltage, the second leakage current is an upper limit value of a leakage current passing through the first switch, and the third leakage current is a lower limit value of a leakage current passing through the second switch.

公开(公告)号：US09755070B2

公开(公告)日：2017-09-05

申请号：US15077927

申请日：2016-03-23

Applicant: DELTA ELECTRONICS, INC.

Inventor： Chao-Feng Cai ,  Jian-Hong Zeng ,  Zeng Li

IPC: H01L29/78 ,  H01L23/50

CPC classification number: H01L29/7826 ,  H01L23/50 ,  H01L24/20 ,  H01L24/24 ,  H01L2224/04105 ,  H01L2224/18 ,  H01L2924/19104

Abstract: A semiconductor packaging structure includes a chip, a first pin, a second pin, and a third pin. The chip includes a first surface, a second surface, a first power switch, and a second switch, and both the first power switch and the second switch include a first terminal and a second terminal. The second surface of the chip is opposite to the first surface of the chip. The first pin does not contact to the second pin. The first terminal of the first power switch of the chip is coupled to the first pin, and the second terminal of the first power switch of the chip is coupled to the third pin. The first terminal of the second power switch of the chip is coupled to the third pin, and the second terminal of the second power switch of the chip is coupled to the second pin.

公开(公告)号：US09698701B2

公开(公告)日：2017-07-04

申请号：US15168235

申请日：2016-05-30

Applicant: DELTA ELECTRONICS, INC.

Inventor： Zeng Li ,  Jun-Cheng Lu ,  Tao Wang ,  Zheng-Fen Wan ,  Zhen-Qing Zhao

IPC: H01L23/495 ,  H01L21/50 ,  H02M7/00 ,  H01L23/498 ,  H01L25/18 ,  H01L25/07 ,  H01L21/48 ,  H01L23/00

CPC classification number: H02M7/003 ,  H01L21/4846 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L25/072 ,  H01L25/18 ,  H01L2224/2732 ,  H01L2224/291 ,  H01L2224/29294 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/32227 ,  H01L2224/48091 ,  H01L2224/48157 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83815 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/1203 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2224/2743 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/32245 ,  H01L2224/48247

Abstract: A power module packaging structure includes a first conducting layer, a first insulating layer, a second conducting layer, a first power device, and a first controlling device. The first insulating layer is disposed above the first conducting layer. The second conducting layer is disposed above the first insulating layer. The first power device is disposed on the first conducting layer. The first controlling device is disposed on the second conducting layer and used for controlling the first power device. The first conducting layer, the second conducting layer, the first power device, and the first controlling device form a loop. A direction of a current which flows through the first conducting layer in the loop is opposite to a direction of a current which flows through the second conducting layer in the loop.