公开(公告)号：US07087532B2

公开(公告)日：2006-08-08

申请号：US10711683

申请日：2004-09-30

申请人： David M Dobuzinsky ,  Jochen C. Beintner ,  Siddhartha Panda

发明人： David M Dobuzinsky ,  Jochen C. Beintner ,  Siddhartha Panda

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/3086 ,  H01L21/3081 ,  H01L21/3088 ,  H01L21/32139 ,  H01L29/66795 ,  H01L29/785

摘要： A process for forming sublithographic structures such as fins employs a hardmask protective layer above a hardmask to absorb damage during a dry etching step, thereby preserving symmetry in the hardmask and eliminating a source of defects.

摘要翻译： 用于形成诸如翅片之类的亚光刻结构的工艺使用硬掩模上方的硬掩模保护层来在干蚀刻步骤期间吸收损伤，由此保持硬掩模中的对称性并消除缺陷源。

公开(公告)号：US20090104776A1

公开(公告)日：2009-04-23

申请号：US11874392

申请日：2007-10-18

申请人： David M. Dobuzinsky ,  Johnathan E. Faltermeier ,  Naoyoshi Kusaba ,  Joyce C. Liu ,  Munir D. Naeem ,  Siddhartha Panda ,  Richard S. Wise ,  Hongwen Yan

发明人： David M. Dobuzinsky ,  Johnathan E. Faltermeier ,  Naoyoshi Kusaba ,  Joyce C. Liu ,  Munir D. Naeem ,  Siddhartha Panda ,  Richard S. Wise ,  Hongwen Yan

IPC分类号： H01L21/4763

CPC分类号： H01L21/76838 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32137 ,  H01L21/32139

摘要： A method for forming lines for semiconductor devices including, depositing a shallow trench isolation (STI) film stack on a silicon substrate, depositing a layer of polysilicon on the STI film stack, depositing a layer of antireflective coating on the layer of polysilicon, developing a phototoresist on the antireflective coating, wherein the photoresist defines a line, etching the layer of antireflective coating and the layer of polysilicon using RIE with a low bias power, removing the photoresist, removing the layer of antireflective coating, etching the STI film stack to form the line, wherein the layer of polysilicon further defines the line.

摘要翻译： 一种用于形成用于半导体器件的线的方法，包括：在硅衬底上沉积浅沟槽隔离（STI）膜堆叠，在所述STI膜堆叠上沉积多晶硅层，在所述多晶硅层上沉积一层抗反射涂层， 在抗反射涂层上光致抗蚀剂，其中光致抗蚀剂限定线，使用具有低偏压功率的RIE蚀刻抗反射涂层和多晶硅层，去除光致抗蚀剂，去除抗反射涂层，蚀刻STI膜叠层以形成 所述线，其中所述多晶硅层进一步限定所述线。

公开(公告)号：US07687829B2

公开(公告)日：2010-03-30

申请号：US12144250

申请日：2008-06-23

申请人： Dureseti Chidambarrao ,  Judson R. Holt ,  Meikei Ieong ,  Qiqing C. Ouyang ,  Siddhartha Panda

发明人： Dureseti Chidambarrao ,  Judson R. Holt ,  Meikei Ieong ,  Qiqing C. Ouyang ,  Siddhartha Panda

IPC分类号： H01L29/04

CPC分类号： H01L29/045 ,  H01L21/823807 ,  H01L29/7843

摘要： A semiconductor structure having improved carrier mobility is provided. The semiconductor structures includes a hybrid oriented semiconductor substrate having at least two planar surfaces of different crystallographic orientation, and at least one CMOS device located on each of the planar surfaces of different crystallographic orientation, wherein each CMOS device has a stressed channel. The present invention also provides methods of fabricating the same. In general terms, the inventive method includes providing a hybrid oriented substrate having at least two planar surfaces of different crystallographic orientation, and forming at least one CMOS device on each of the planar surfaces of different crystallographic orientation, wherein each CMOS device has a stressed channel.

摘要翻译： 提供了具有改进的载流子迁移率的半导体结构。 半导体结构包括具有不同晶体取向的至少两个平坦表面的混合取向半导体衬底，以及位于不同结晶取向的每个平面上的至少一个CMOS器件，其中每个CMOS器件具有应力通道。 本发明还提供了制造该方法的方法。 一般来说，本发明的方法包括提供具有至少两个具有不同晶体取向的平面表面的混合取向衬底，以及在不同结晶取向的每个平面上形成至少一个CMOS器件，其中每个CMOS器件具有受压沟道 。

公开(公告)号：US20080179627A1

公开(公告)日：2008-07-31

申请号：US11669902

申请日：2007-01-31

申请人： Meikei Ieong ,  Xiao Hu Liu ,  Qiqing Christine Ouyang ,  Siddhartha Panda ,  Haizhou Yin

发明人： Meikei Ieong ,  Xiao Hu Liu ,  Qiqing Christine Ouyang ,  Siddhartha Panda ,  Haizhou Yin

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/78687

摘要： NMOS and PMOS device structures with separately strained channel regions and methods of their fabrication are disclosed. The source and the drain of the NMOS device is epitaxially grown of a material which causes a shift in the strain of the NMOS device channel in the tensile direction. While, the source and the drain of the PMOS device is epitaxially grown of a material which causes a shift in the strain of the PMOS device channel in the compressive direction.

摘要翻译： 公开了具有单独应变通道区域的NMOS和PMOS器件结构及其制造方法。 NMOS器件的源极和漏极由引起NMOS器件沟道在拉伸方向上的应变移动的材料外延生长。 而PMOS器件的源极和漏极是外延生长的，这种材料导致PMOS器件沟道在压缩方向上的应变移动。

公开(公告)号：US20080090370A1

公开(公告)日：2008-04-17

申请号：US11548870

申请日：2006-10-12

申请人： Thomas W. Dyer ,  Sunfei Fang ,  Jiang Yan ,  Siddhartha Panda ,  Yong Meng Lee

发明人： Thomas W. Dyer ,  Sunfei Fang ,  Jiang Yan ,  Siddhartha Panda ,  Yong Meng Lee

IPC分类号： H01L21/331

CPC分类号： H01L21/32 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656

摘要： A method forms a gate conductor over a substrate, forms spacers (e.g., nitride spacers) on sides of the gate conductor, and implants an impurity into exposed regions of the substrate not protected by the gate conductor and the spacers. Then the method forms a silicide on surfaces of the exposed regions of the substrate. The method forms a conformal protective layer (e.g., an oxide or other similar material) over the silicide, the spacers, and the gate conductor. Next, the method forms a non-conformal sacrificial layer (e.g., nitride or other material that can be selectively removed with respect to the protective layer) over the protective layer. A subsequent partial etching process partially etches the sacrificial layer such that relatively thinner regions of the sacrificial layer that are over the spacers are completely removed and the relatively thicker regions of the sacrificial layer that are over the substrate are not removed. The next step in the method removes only those portions of the protective layer that cover the spacers, without removing the portions of the protective layer that cover the silicide. As the spacers are now exposed and the silicide is protected by the protective and sacrificial layers, the method can safely remove the spacers without affecting the silicide.

公开(公告)号：US20070293016A1

公开(公告)日：2007-12-20

申请号：US11424076

申请日：2006-06-14

申请人： Zhijiong Luo ,  Hung Y. Ng ,  Nivo Rovedo ,  Phung T. Nguyen ,  William C. Wille ,  Richard Lindsay ,  Zhao Lun ,  Yung Fu Chong ,  Siddhartha Panda

发明人： Zhijiong Luo ,  Hung Y. Ng ,  Nivo Rovedo ,  Phung T. Nguyen ,  William C. Wille ,  Richard Lindsay ,  Zhao Lun ,  Yung Fu Chong ,  Siddhartha Panda

IPC分类号： H01L21/76

CPC分类号： H01L21/823892 ,  H01L21/76218 ,  H01L21/76232 ,  H01L21/823878

摘要： A semiconductor structure includes a base semiconductor substrate having a doped region located therein, and an epitaxial region located over the doped region. The semiconductor structure also includes a final isolation region located with the doped region and the epitaxial region. The final isolation region has a greater linewidth within the doped region than within the epitaxial region. A method for fabricating the semiconductor structure provides for forming the doped region prior to the epitaxial region. The doped region may be formed with reduced well implant energy and reduced lateral straggle. The final isolation region with the variable linewidth provides a greater effective isolation depth than an actual trench isolation depth.

摘要翻译： 半导体结构包括具有位于其中的掺杂区的基极半导体衬底和位于掺杂区上方的外延区。 半导体结构还包括位于掺杂区和外延区的最后隔离区。 最后的隔离区域在掺杂区域内具有比外延区域内更大的线宽。 制造半导体结构的方法提供了在外延区之前形成掺杂区。 掺杂区域可以形成为具有减少的良好注入能量和减小的横向分层。 具有可变线宽的最终隔离区域提供比实际沟槽隔离深度更大的有效隔离深度。

公开(公告)号：US20070056930A1

公开(公告)日：2007-03-15

申请号：US11162550

申请日：2005-09-14

申请人： Seiji Iseda ,  Siddhartha Panda ,  Michael Sievers ,  Richard Wise

发明人： Seiji Iseda ,  Siddhartha Panda ,  Michael Sievers ,  Richard Wise

IPC分类号： C03C25/68 ,  B44C1/22 ,  H01L21/461 ,  C23F1/00

CPC分类号： H01L21/32137

摘要： Polysilicon etching methods are disclosed that employ a gas flow including perfluorocyclopentene (C5F8) and nitrogen trifluoride (NF3). The etching methods achieved a substantially vertical profile and smoother surfaces, and may achieve a 3sigma variation as low as 3.0 nm.

摘要翻译： 公开了采用包括全氟环戊烯（C 5 H 5 F 8 N）和三氟化氮（NF 3 3））的气流的多晶硅蚀刻方法。 蚀刻方法实现了基本垂直的轮廓和更平滑的表面，并且可以实现低至3.0nm的3σ变化。

公开(公告)号：US20070048980A1

公开(公告)日：2007-03-01

申请号：US11161964

申请日：2005-08-24

申请人： Judson Holt ,  Siddhartha Panda

发明人： Judson Holt ,  Siddhartha Panda

IPC分类号： H01L21/20 ,  H01L21/302

CPC分类号： H01L21/02057 ,  H01L21/02367 ,  H01L21/02499 ,  H01L21/02518 ,  H01L21/02658

摘要： A method for preparing a substrate for epitaxial crystal growth thereon includes performing a reactive ion etch (RIE) on a selected area of the substrate to be prepared for epitaxial crystal growth, discontinuing the introduction of an etchant species associated with the RIE, and introducing a monolayer forming species into a chamber containing the substrate. The neutral species is selected so as to form a passivating monolayer on the selected area of the substrate, wherein the monolayer is resistant to the formation of native oxide thereon.

摘要翻译： 制备用于外延晶体生长的衬底的方法包括在待制备用于外延晶体生长的衬底的选定区域上执行反应离子蚀刻（RIE），停止引入与RIE相关联的蚀刻剂物质，并引入 单层形成物质进入含有底物的室。 选择中性物质以在底物的选定区域上形成钝化单层，其中单层对其上形成天然氧化物具有抗性。

公开(公告)号：US20060065914A1

公开(公告)日：2006-03-30

申请号：US10711637

申请日：2004-09-29

申请人： Huajie Chen ,  Dureseti Chidambarrao ,  Sang-Hyun Oh ,  Siddhartha Panda ,  Werner Rausch ,  Tsutomu Sato ,  Henry Utomo

发明人： Huajie Chen ,  Dureseti Chidambarrao ,  Sang-Hyun Oh ,  Siddhartha Panda ,  Werner Rausch ,  Tsutomu Sato ,  Henry Utomo

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L21/28052 ,  H01L21/28079 ,  H01L21/7624 ,  H01L29/1045 ,  H01L29/165 ,  H01L29/4933 ,  H01L29/495 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： A field effect transistor (“FET”) is provided which includes a gate stack overlying a single-crystal semiconductor region of a substrate, a pair of first spacers disposed over sidewalls of said gate stack, and a pair of regions consisting essentially of a single-crystal semiconductor alloy which are disposed on opposite sides of the gate stack. Each of the semiconductor alloy regions is spaced a first distance from the gate stack. The source region and drain region of the FET are at least partly disposed in respective ones of the semiconductor alloy regions, such that the source region and the drain region are each spaced a second distance from the gate stack by a first spacer of the pair of first spacers, the second distance being different from the first distance.

公开(公告)号：US20100187636A1

公开(公告)日：2010-07-29

申请号：US12754939

申请日：2010-04-06

申请人： Haining S. Yang ,  Siddhartha Panda

发明人： Haining S. Yang ,  Siddhartha Panda

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L27/1203 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure and a method of fabricating the same in which strain enhancement is achieved for both nFET and pFET devices is provided. In particular, the present invention provides at least one spacerless FET for stronger strain enhancement and defect reduction. The at least one spacerless FET can be a pFET, an nFET, or a combination thereof, with spacerless pFETs being particularly preferred since pFETs are generally fabricated to have a greater width than nFETs. The at least one spacerless FET allows to provide a stress inducing liner in closer proximity to the device channel than prior art structures including FETs having spacers. The spacerless FET is achieved without negatively affecting the resistance of the corresponding silicided source/drain diffusion contacts, which do not encroach underneath the spacerless FET.

摘要翻译： 提供半导体结构及其制造方法，其中对nFET和pFET器件实现应变增强。 特别地，本发明提供了用于更强应变增强和缺陷减少的至少一个无间隔型FET。 至少一个无衬垫FET可以是pFET，nFET或其组合，其中无间隙pFET是特别优选的，因为pFET通常制造成具有比nFET更大的宽度。 至少一个无间隔FET允许提供比包括具有间隔物的FET的现有技术结构更靠近器件沟道的应力诱导衬垫。 实现了无间隔FET，而不会不利地影响相应的硅化物源极/漏极扩散触点的电阻，其不会侵入无间隔FET的下方。