Method of forming a semiconductor device barrier layer
    1.
    发明授权
    Method of forming a semiconductor device barrier layer 有权
    形成半导体器件阻挡层的方法

    公开(公告)号:US06451181B1

    公开(公告)日:2002-09-17

    申请号:US09261879

    申请日:1999-03-02

    IPC分类号: C23C1434

    摘要: A method for forming an improved copper inlaid interconnect (FIG. 11) begins by performing an RF preclean operation (408) on the inlaid structure in a chamber (10). The RF preclean rounds corners (210a and 206a) of the structure to reduce voiding and improve step coverage while not significantly removing copper atoms from the underlying exposed copper interconnects surfaces (202a). A tantalum barrier (220) is then deposited where one portion of the tantalum barrier is more tensile than another portion of the tantalum barrier. After formation of the barrier layer (220), a copper seed layer (222) is formed over a top of the barrier layer. The copper layer is formed while clamping the wafer with an improved clamp (85) which reduces copper peeling and contamination at wafer edges. Copper electroplating and chemical mechanical polishing (CMP) processes are then used to complete the copper interconnect structure.

    摘要翻译: 用于形成改进的铜镶嵌互连(图11)的方法开始于在腔室(10)中的镶嵌结构上执行RF预清洗操作(408)。 RF预清洁器围绕结构的角部(210a和206a),以减少空隙并改善步骤覆盖,同时不显着地从下面暴露的铜互连表面(202a)去除铜原子。 然后沉积钽屏障(220),其中一部分钽屏障比钽屏障的另一部分更具拉伸力。 在形成阻挡层(220)之后,在阻挡层的顶部上形成铜籽晶层(222)。 在使用改进的夹具(85)夹紧晶片的同时形成铜层,其减少了在晶片边缘处的铜剥离和污染。 然后使用铜电镀和化学机械抛光(CMP)工艺来完成铜互连结构。

    Method for forming a copper interconnect using a multi-platen chemical mechanical polishing (CMP) process
    5.
    发明授权
    Method for forming a copper interconnect using a multi-platen chemical mechanical polishing (CMP) process 有权
    使用多台板化学机械抛光(CMP)工艺形成铜互连的方法

    公开(公告)号:US06274478B1

    公开(公告)日:2001-08-14

    申请号:US09352136

    申请日:1999-07-13

    IPC分类号: H01L214763

    摘要: A copper interconnect polishing process begins by polishing (17) a bulk thickness of copper (63) using a first platen. A second platen is then used to remove (19) a thin remaining interfacial copper layer to expose a barrier film (61). Computer control (21) monitors polish times of the first and second platen and adjusts these times to improve wafer throughput. One or more platens and/or the wafer is rinsed (20) between the interfacial copper polish and the barrier polish to reduce slurry cross contamination. A third platen and slurry is then used to polish away exposed portions of the barrier (61) to complete polishing of the copper interconnect structure. A holding tank that contains anti-corrosive fluid is used to queue the wafers until subsequent scrubbing operations (25). A scrubbing operation (25) that is substantially void of light is used to reduce photovoltaic induced corrosion of copper in the drying chamber of the scrubber.

    摘要翻译: 铜互连抛光工艺通过使用第一压板抛光(17)铜(63)的体积厚度开始。 然后使用第二压板来去除(19)薄的剩余界面铜层以暴露阻挡膜(61)。 计算机控制(21)监测第一和第二压板的抛光时间并调整这些时间以提高晶片的吞吐量。 一个或多个压板和/或晶片在界面铜抛光剂和阻隔抛光剂之间漂洗(20),以减少淤浆交叉污染。 然后使用第三压板和浆料抛光掉屏障(61)的暴露部分以完成铜互连结构的抛光。 使用含有防腐蚀液体的储存罐将晶片排队,直到后续的擦洗操作(25)。 使用基本上无光的擦洗操作(25)用于减少洗涤器的干燥室中的铜的光伏诱发的腐蚀。