公开(公告)号：US20110272024A1

公开(公告)日：2011-11-10

申请号：US13076295

申请日：2011-03-30

申请人： Dongwon Choi ,  Michael P. Stewart ,  Li Xu ,  Hemant P. Mungekar ,  Sunhom Paak ,  Kenneth MacWilliams

发明人： Dongwon Choi ,  Michael P. Stewart ,  Li Xu ,  Hemant P. Mungekar ,  Sunhom Paak ,  Kenneth MacWilliams

IPC分类号： H01L31/0232 ,  H01L31/18 ,  C23C16/34 ,  C23C16/50 ,  C23C16/52 ,  H01L31/0216 ,  H01L21/66

CPC分类号： H01L31/02168 ,  H01L31/068 ,  H01L31/1868 ,  Y02E10/547 ,  Y02P70/521

摘要： Embodiments of the invention include a solar cell and methods of forming a solar cell. Specifically, the methods may be used to form a passivation/anti-reflection layer having combined functional and optical gradient properties on a solar cell substrate. The methods may include flowing a first process gas mixture into a process volume within a processing chamber generating plasma in the processing chamber at a power density of greater than 0.65 W/cm2 depositing a silicon nitride-containing interface sub-layer on a solar cell substrate in the process volume, flowing a second process gas mixture into the process volume, and depositing a silicon nitride-containing bulk sub-layer on the silicon nitride-containing interface sub-layer.

摘要翻译： 本发明的实施例包括太阳能电池和形成太阳能电池的方法。 具体地，可以使用这些方法来形成在太阳能电池基板上具有组合的功能和光学梯度特性的钝化/抗反射层。 所述方法可以包括将第一工艺气体混合物流入处理室内的处理容积，所述处理室在处理室中以大于0.65W / cm 2的功率密度产生等离子体，将含氮化硅的界面子层沉积在太阳能电池基板 在处理体积中，使第二工艺气体混合物流入处理体积，以及在含氮化硅的界面子层上沉积含氮化硅的体层状层。

公开(公告)号：US20090004875A1

公开(公告)日：2009-01-01

申请号：US12163888

申请日：2008-06-27

申请人： Meihua Shen ,  Diana Xiaobing Ma ,  Wendy H. Yeh ,  Kenneth MacWilliams ,  Wei Liu ,  Thorsten B. Lill

发明人： Meihua Shen ,  Diana Xiaobing Ma ,  Wendy H. Yeh ,  Kenneth MacWilliams ,  Wei Liu ,  Thorsten B. Lill

IPC分类号： H01L21/308

CPC分类号： H01L21/0337

摘要： Methods for forming an ultra thin structure using a method that includes trimming a mask layer during an etching process are provided. The embodiments described herein may be advantageously utilized to fabricate a submicron structure on a substrate having a critical dimension less than 55 nm and beyond. In one embodiment, a method of forming a submicron structure on a substrate may include providing a substrate having a patterned photoresist layer disposed on a film stack into an etch chamber, wherein the film stack includes at least a hardmask layer disposed on an underlying layer, trimming the photoresist layer to a first predetermined critical dimension, etching the hardmask layer through openings defined by the trimmed photoresist layer, trimming the hardmask layer to a second predetermined critical dimension, and etching the underlying layer through openings defined by the trimmed hardmask layer.

摘要翻译： 提供了使用包括在蚀刻处理期间修整掩模层的方法来形成超薄结构的方法。 本文描述的实施例可有利地用于在临界尺寸小于55nm及以上的衬底上制造亚微米结构。 在一个实施例中，在衬底上形成亚微米结构的方法可以包括提供具有设置在膜堆叠上的图案化光致抗蚀剂层进入蚀刻室的衬底，其中所述膜堆叠包括至少设置在下层上的硬掩模层， 将光致抗蚀剂层修剪到第一预定临界尺寸，通过由修剪的光致抗蚀剂层限定的开口蚀刻硬掩模层，将硬掩模层修剪到第二预定临界尺寸，以及通过由修剪的硬掩模层限定的开孔蚀刻下层。

公开(公告)号：US08293460B2

公开(公告)日：2012-10-23

申请号：US12339836

申请日：2008-12-19

申请人： Hui W. Chen ,  Chorng-Ping Chang ,  Yongmei Chen ,  Huixiong Dai ,  Jiahua Yu ,  Susie X. Yang ,  Xumou Xu ,  Christopher D. Bencher ,  Raymond Hoiman Hung ,  Michael P. Duane ,  Christopher Siu Wing Ngai ,  Jen Shu ,  Kenneth MacWilliams

发明人： Hui W. Chen ,  Chorng-Ping Chang ,  Yongmei Chen ,  Huixiong Dai ,  Jiahua Yu ,  Susie X. Yang ,  Xumou Xu ,  Christopher D. Bencher ,  Raymond Hoiman Hung ,  Michael P. Duane ,  Christopher Siu Wing Ngai ,  Jen Shu ,  Kenneth MacWilliams

IPC分类号： G03F7/20

CPC分类号： G03F7/11 ,  G03F7/091 ,  G03F7/2022

摘要： Methods to pattern features in a substrate layer by exposing a photoresist layer more than once. In one embodiment, a single reticle may be exposed more than once with an overlay offset implemented between successive exposures to reduce the half pitch of the reticle. In particular embodiments, these methods may be employed to reduce the half pitch of the features printed with 65 nm generation lithography equipment to achieve 45 nm lithography generation CD and pitch performance.

摘要翻译： 通过不止一次地曝光光致抗蚀剂层来对衬底层中的特征进行图案化的方法。 在一个实施例中，单个掩模版可以在连续曝光之间实现的覆盖偏移曝光不止一次以减小掩模版的半间距。 在特定实施例中，可以使用这些方法来减少用65nm生成光刻设备印刷的特征的半间距，以实现45nm光刻产生CD和间距性能。

公开(公告)号：US20090309230A1

公开(公告)日：2009-12-17

申请号：US12336884

申请日：2008-12-17

申请人： ZHENJIANG CUI ,  Mehul Naik ,  Christopher D. Bencher ,  Kenneth MacWilliams

发明人： ZHENJIANG CUI ,  Mehul Naik ,  Christopher D. Bencher ,  Kenneth MacWilliams

IPC分类号： H01L21/768 ,  H01L23/535

CPC分类号： H01L23/5222 ,  H01L21/02115 ,  H01L21/02271 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/3146 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76832 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods for patterning films and their resulting structures. In an embodiment, an amorphous carbon mask is formed over a substrate, such as a damascene layer. A spacer layer is deposited over the amorphous carbon mask and the spacer layer is etched to form a spacer and to expose the amorphous carbon mask. The amorphous carbon mask is removed selectively to the spacer to expose the substrate layer. A gap fill layer is deposited around the spacer to cover the substrate layer but expose the spacer. The spacer is removed selectively to form a gap fill mask over the substrate. The pattern of the gap fill mask is transferred, in one implementation, into a damascene layer to remove at least a portion of an IMD and form an air gap.

摘要翻译： 膜图案及其结果的方法。 在一个实施方案中，在诸如镶嵌层的基底上形成无定形碳掩模。 在无定形碳掩模上沉积间隔层，并且蚀刻间隔层以形成间隔物并暴露无定形碳掩模。 无定形碳掩模被选择性地去除到间隔物以暴露衬底层。 间隔填充层沉积在间隔物周围以覆盖基底层，但暴露间隔物。 选择性地移除间隔物以在衬底上形成间隙填充掩模。 间隙填充掩模的图案在一个实施方式中转移到镶嵌层中以去除IMD的至少一部分并形成气隙。

公开(公告)号：US07811924B2

公开(公告)日：2010-10-12

申请号：US12336884

申请日：2008-12-17

申请人： Zhenjiang Cui ,  Mehul Naik ,  Christopher D. Bencher ,  Kenneth MacWilliams

发明人： Zhenjiang Cui ,  Mehul Naik ,  Christopher D. Bencher ,  Kenneth MacWilliams

IPC分类号： H01L21/4763

CPC分类号： H01L23/5222 ,  H01L21/02115 ,  H01L21/02271 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/3146 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76832 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods for patterning films and their resulting structures. In an embodiment, an amorphous carbon mask is formed over a substrate, such as a damascene layer. A spacer layer is deposited over the amorphous carbon mask and the spacer layer is etched to form a spacer and to expose the amorphous carbon mask. The amorphous carbon mask is removed selectively to the spacer to expose the substrate layer. A gap fill layer is deposited around the spacer to cover the substrate layer but expose the spacer. The spacer is removed selectively to form a gap fill mask over the substrate. The pattern of the gap fill mask is transferred, in one implementation, into a damascene layer to remove at least a portion of an IMD and form an air gap.

摘要翻译： 膜图案及其结果的方法。 在一个实施方案中，在诸如镶嵌层的基底上形成无定形碳掩模。 在无定形碳掩模上沉积间隔层，并且蚀刻间隔层以形成间隔物并暴露无定形碳掩模。 无定形碳掩模被选择性地去除到间隔物以暴露衬底层。 间隔填充层沉积在间隔物周围以覆盖基底层，但暴露间隔物。 选择性地移除间隔物以在衬底上形成间隙填充掩模。 间隙填充掩模的图案在一个实施方式中转移到镶嵌层中以去除IMD的至少一部分并形成气隙。

公开(公告)号：US20060166485A1

公开(公告)日：2006-07-27

申请号：US11389428

申请日：2006-03-23

申请人： Jay Uglow ,  Nicolas Bright ,  Dave Hemker ,  Kenneth MacWilliams ,  Jeffrey Benzing ,  Timothy Archer

发明人： Jay Uglow ,  Nicolas Bright ,  Dave Hemker ,  Kenneth MacWilliams ,  Jeffrey Benzing ,  Timothy Archer

IPC分类号： H01L21/4763

CPC分类号： H01L21/76835 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02304 ,  H01L21/31116 ,  H01L21/314 ,  H01L21/31633 ,  H01L21/76807 ,  H01L21/76822

摘要： A dielectric structure and method for making a dielectric structure for dual-damascene applications over a substrate are provided. The method includes forming a barrier layer over the substrate, forming an inorganic dielectric layer over the barrier layer, and forming a low dielectric constant layer over the inorganic dielectric layer. In this preferred example, the method also includes forming a trench in the low dielectric constant layer using a first etch chemistry. The etching is timed to etch through a partial thickness of the low dielectric constant layer and the first etch chemistry is optimized to a selected low dielectric constant material. The method further includes forming a via hole in the inorganic dielectric layer using a second etch chemistry, such that the via is within the trench. In a specific example, the inorganic dielectric layer can be an un-doped TEOS oxide or a fluorine doped oxide, and the low dielectric constant layer can be a carbon doped oxide (C-oxide) or other low K dielectrics.