公开(公告)号：US4259779A

公开(公告)日：1981-04-07

申请号：US827373

申请日：1977-08-24

申请人： Alfred C. Ipri ,  Doris W. Flatley

发明人： Alfred C. Ipri ,  Doris W. Flatley

IPC分类号： H01L29/78 ,  B01J17/00

CPC分类号： H01L29/78 ,  Y10S257/906 ,  Y10S438/953

摘要： The radiation resistance of an MOS transistor is improved by making the transistor in a manner such that, after the gate insulation layer is formed, all further steps are carried out at a relatively low temperature, i.e., less than about 900.degree. C. The source and drain regions are preferably formed by ion implantation with very little or no post implant thermal activation, and the metallization is applied by low temperature techniques.

摘要翻译： 通过使晶体管以形成栅极绝缘层的方式来提高MOS晶体管的辐射电阻，所有其它步骤在相对较低的温度（即小于约900℃）下进行。源 并且漏极区优选通过离子注入形成，具有非常少的或没有后植入物热激活，并且金属化通过低温技术施加。

公开(公告)号：US4104087A

公开(公告)日：1978-08-01

申请号：US785481

申请日：1977-04-07

申请人： Alfred C. Ipri ,  Doris W. Flatley

发明人： Alfred C. Ipri ,  Doris W. Flatley

IPC分类号： H01L21/86 ,  H01L21/265

CPC分类号： H01L21/86

摘要： MNOS memory circuit fabrication problems that result in leakage, memory device depletion mode switching and leakage paths at the edges of silicon islands are eliminated by a production process in which deposited and thermal oxides are used as a diffusion mask on the island edges, selective control of the threshold level of the memory device is achieved by ion implantation, and a thick oxide is grown on the silicon island edges to control charge injection.

摘要翻译： 导致泄漏，存储器件耗尽模式切换和硅岛边缘处的泄漏路径的MNOS存储器电路制造问题通过其中沉积和热氧化物用作岛边缘上的扩散掩模的生产工艺被消除，选择性控制 通过离子注入实现存储器件的阈值电平，并且在硅岛边缘上生长厚氧化物以控制电荷注入。

公开(公告)号：US4722912A

公开(公告)日：1988-02-02

申请号：US856277

申请日：1986-04-28

申请人： Doris W. Flatley ,  Alfred C. Ipri

发明人： Doris W. Flatley ,  Alfred C. Ipri

IPC分类号： H01L21/316 ,  H01L21/336 ,  H01L21/86 ,  H01L27/08

CPC分类号： H01L29/66757 ,  H01L21/02238 ,  H01L21/31662 ,  H01L21/86 ,  H01L29/66772

摘要： A method for forming a layer of silicon dioxide over a silicon island on an insulating surface wherein the layer on top of the island is thinner than on the sidewalls is disclosed. The silicon island is oxidized and a silicon layer is deposited thereover. The layer of silicon is oxidized and the oxide layer is anisotropically etched until the top surface of the island is exposed, leaving oxide only on the sidewalls of the island. The exposed portion of the island is then oxidized to form a thin layer of gate oxide thereon. A conductive polycrystalline silicon electrode is deposited on the oxide-covered island. The disclosed method is particularly useful in the formation of MOSFETs.

摘要翻译： 公开了一种在绝缘表面上的硅岛上形成二氧化硅层的方法，其中岛顶部的层比在侧壁上薄。 硅岛氧化，硅层沉积在其上。 硅层被氧化，并且各向异性蚀刻氧化层，直到岛的顶表面露出，仅在岛的侧壁上留下氧化物。 然后，岛的暴露部分被氧化以在其上形成薄层的栅极氧化物。 导电多晶硅电极沉积在氧化物覆盖的岛上。 所公开的方法在形成MOSFET中特别有用。

公开(公告)号：US4658495A

公开(公告)日：1987-04-21

申请号：US856278

申请日：1986-04-28

申请人： Doris W. Flatley ,  Alfred C. Ipri

发明人： Doris W. Flatley ,  Alfred C. Ipri

IPC分类号： H01L21/316 ,  H01L21/336 ,  H01L21/86 ,  H01L21/473

CPC分类号： H01L29/66757 ,  H01L21/02238 ,  H01L21/31662 ,  H01L21/86 ,  H01L29/66772 ,  Y10S148/15 ,  Y10S438/911 ,  Y10S438/981

摘要： A method for forming a layer of silicon dioxide over a silicon island on an insulating surface wherein the layer on top of the island is thinner than on the sidewalls is disclosed. The silicon island is oxidized and a silicon layer is deposited thereover. A layer of planarizing material is deposited over the silicon layer. The planarizing layer is anisotropically etched until the surface of the silicon layer overlying the island is exposed. The silicon layer is in turn etched until the surface of the oxide layer overlying the island is exposed. The remaining planarizing material is removed and the remaining silicon layer is oxidized. The thickness of the gate oxide layer on top of the island may be controlled by again exposing the island surface and reoxidizing to a predetermined thickness. A conductive polycrystalline silicon electrode is deposited on the oxide-covered island. The disclosed method is particularly useful in the formation of MOSFETs.

摘要翻译： 公开了一种在绝缘表面上的硅岛上形成二氧化硅层的方法，其中岛顶部的层比在侧壁上薄。 硅岛氧化，硅层沉积在其上。 平坦化材料层沉积在硅层上。 各向异性蚀刻平坦化层，直到覆盖在岛上的硅层的表面露出。 再次蚀刻硅层直至覆盖岛上的氧化物层的表面露出。 剩余的平坦化材料被去除，剩余的硅层被氧化。 可以通过再次暴露岛表面并再氧化至预定厚度来控制岛顶上的栅极氧化物层的厚度。 导电多晶硅电极沉积在氧化物覆盖的岛上。 所公开的方法在形成MOSFET中特别有用。

公开(公告)号：US4804640A

公开(公告)日：1989-02-14

申请号：US104451

申请日：1987-10-05

申请人： Grzegorz Kaganowicz ,  John W. Robinson ,  Alfred C. Ipri

发明人： Grzegorz Kaganowicz ,  John W. Robinson ,  Alfred C. Ipri

IPC分类号： C23C14/02 ,  C23C14/08 ,  H01L21/28 ,  H01L29/51 ,  H01L21/473

CPC分类号： H01L29/513 ,  C23C14/027 ,  C23C14/08 ,  C23C14/081 ,  H01L21/28273 ,  H01L29/517

摘要： A process of forming a three region dielectric film on silicon and a semiconductor device employing such a film are disclosed. Silicon is oxidized in an oxygen-containing ambient. The oxidation step forms a first region of silicon oxide. Once oxidation has begun, reactive sputtering of aluminum in an oxygen plasma is initiated. This forms a second region of said dielectric film which comprises a mixture of silicon and aluminum oxides. A third region comprising substantially aluminum oxide is formed by the continuing reactive sputtering step.A semiconductor device comprising said three region dielectric film interposed between an electrode and a semiconductor body has little or no shift in threshold voltage providing good stability and can be fabricated in substantially less time and/or at lower temperatures than prior art methods.

摘要翻译： 公开了一种在硅上形成三区电介质膜的工艺和采用这种膜的半导体器件。 硅在含氧环境中被氧化。 氧化步骤形成氧化硅的第一区域。 一旦氧化开始，则开始在氧等离子体中的铝的反应溅射。 这形成了包括硅和氧化铝的混合物的所述电介质膜的第二区域。 通过连续反应溅射步骤形成包含基本上氧化铝的第三区域。 包括介于电极和半导体本体之间的所述三区电介质薄膜的半导体器件几乎没有或没有阈值电压的偏移提供良好的稳定性，并且可以在比现有技术方法更短的时间和/或更低的温度下制造。

公开(公告)号：US4791464A

公开(公告)日：1988-12-13

申请号：US048704

申请日：1987-05-12

申请人： Alfred C. Ipri ,  Dora Plus

发明人： Alfred C. Ipri ,  Dora Plus

IPC分类号： H01L27/12 ,  H01L29/786 ,  H01L29/78

CPC分类号： H01L27/12 ,  H01L29/78609

摘要： A semiconductor device comprising an island of semiconductor material disposed on an insulating substrate is disclosed. A MOS transistor is formed in the semiconductor island such that the gate electrode extends over the sidewalls of the island. Diodes are formed between the source and drain regions and the portions of the channel region along the sidewalls to electrically isolate the top transistor from the parasitic edge transistors.

摘要翻译： 公开了一种包括设置在绝缘基板上的半导体材料岛的半导体器件。 MOS晶体管形成在半导体岛中，使得栅电极延伸在岛的侧壁上。 在源极和漏极区域之间以及沿着侧壁的沟道区域的部分形成二极管以将顶部晶体管与寄生边缘晶体管电隔离。

公开(公告)号：US4530149A

公开(公告)日：1985-07-23

申请号：US489307

申请日：1985-04-28

申请人： Lubomir L. Jastrzebski ,  Alfred C. Ipri ,  Achilles G. Kokkas

发明人： Lubomir L. Jastrzebski ,  Alfred C. Ipri ,  Achilles G. Kokkas

IPC分类号： H01L27/00 ,  H01L21/20 ,  H01L21/28 ,  H01L27/06 ,  H01L27/11 ,  H01L29/423 ,  H01L29/78 ,  H01L21/205

CPC分类号： H01L29/7827 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/28 ,  H01L27/0688 ,  H01L27/1104 ,  H01L29/66666 ,  H01L29/4236

摘要： A vertical IGFET device is formed on a substrate which includes a monocrystalline silicon portion at a surface thereof. An apertured insulated gate electrode is disposed on the substrate surface such that an area of monocrystalline silicon is exposed through the aperture. An epitaxial silicon region extends from the substrate surface within the gate electrode aperture and is appropriately doped such that a predetermined voltage applied to the insulated gate electrode forms a channel region in the epitaxial region adjacent thereto. The vertical IGFET is fabricated by a self-aligned technique, wherein the insulated gate electrode includes a first, underlying insulating layer and a second, overlying insulating layer. The second insulating layer protects the gate electrode when the first insulating layer is defined.

摘要翻译： 在包括其表面的单晶硅部分的基板上形成垂直IGFET器件。 多孔绝缘栅电极设置在衬底表面上，使得单晶硅的面积通过该孔露出。 外延硅区域从栅电极孔内的衬底表面延伸并被适当地掺杂，使得施加到绝缘栅电极的预定电压在与其相邻的外延区域中形成沟道区。 垂直IGFET通过自对准技术制造，其中绝缘栅电极包括第一下层绝缘层和第二覆盖绝缘层。 当限定第一绝缘层时，第二绝缘层保护栅电极。

公开(公告)号：US4282556A

公开(公告)日：1981-08-04

申请号：US41085

申请日：1979-05-21

申请人： Alfred C. Ipri

发明人： Alfred C. Ipri

IPC分类号： H01L27/02 ,  H01L29/423 ,  H03F1/52 ,  H03K17/0812 ,  H02H3/22

CPC分类号： H01L29/42384 ,  H01L27/0266 ,  H03F1/523 ,  H03K17/08122

摘要： An input protection device comprising at least one pair of N and P type MOSFETs having their conduction paths series connected between a source of operating potential and the input of the circuit to be protected. Another variation includes a second pair of similarly connected N and P type MOSFETs with one pair connected between the input to be protected and the most negative source of operating potential while the second pair is connected between the most positive source of operating potential and the input to be protected.

摘要翻译： 一种输入保护装置，包括至少一对N型和P型MOSFET，它们的导通路径串联连接在工作电位源和待保护电路的输入端之间。 另一种变化包括第二对类似连接的N型和P型MOSFET，其中一对连接在待保护的输入端和最负的工作电位之间，而第二对连接在最正的工作电源和输入端 被保护。

公开(公告)号：US06417825B1

公开(公告)日：2002-07-09

申请号：US09200513

申请日：1998-11-25

申请人： Roger G. Stewart ,  Alfred C. Ipri

发明人： Roger G. Stewart ,  Alfred C. Ipri

IPC分类号： G09G330

CPC分类号： G09G3/30 ,  G09G3/2011 ,  G09G3/2018 ,  G09G3/2051 ,  G09G2300/0809 ,  G09G2300/0842

摘要： An emissive display device such as an active matrix electroluminescent display (AMEL display) has an improved method of operation. The AMEL display produces gray scale operation comprising an array of pixels, each pixel including a first transistor having its gate connected to a select line, its source connected to a data line, and its drain connected to the gate of a second transistor. The second transistor has its source adapted to receive a ramped voltage level, and its drain connected to a first electrode of an electroluminescent cell. The electroluminescent cell has a second electrode connected to an alternating current high voltage power source, wherein the electroluminescent cell is illuminated, when the ramp voltage level is less than a voltage level on the gate of the second transistor. The ramp voltage level is increased linearly during a frame duration, and the alternating current high voltage power source is on continuously during the same frame duration. The alternating current high voltage power source may also be varied in amplitude from a minimum peak-to-peak value to a maximum peak-to-peak value during the frame duration.

摘要翻译： 诸如有源矩阵电致发光显示器（AMEL显示器）的发射显示装置具有改进的操作方法。 AMEL显示器产生包括像素阵列的灰度级操作，每个像素包括其栅极连接到选择线的第一晶体管，其源极连接到数据线，其漏极连接到第二晶体管的栅极。 第二晶体管的源极适于接收斜坡电压电平，其漏极连接到电致发光单元的第一电极。 电致发光单元具有连接到交流高压电源的第二电极，其中当斜坡电压电平小于第二晶体管的栅极上的电压电平时，电致发光单元被照亮。 斜坡电压电平在帧持续时间内线性增加，并且交流电压高电压电源在相同的帧持续时间期间连续地连续。 在帧持续时间期间，交流电压高压电源也可以从最小峰 - 峰值到最大峰 - 峰值的幅度变化。

公开(公告)号：US5076667A

公开(公告)日：1991-12-31

申请号：US471566

申请日：1990-01-29

申请人： Roger G. Stewart ,  Alfred C. Ipri

发明人： Roger G. Stewart ,  Alfred C. Ipri

IPC分类号： G02F1/1345

CPC分类号： G02F1/1345

摘要： A Liquid Crystal Display device has first and second transparent substrates with a liquid crystal material sealed therebetween; a centrally disposed optically active display region having a matrix of pixels and a first and second scanner, and a transparent common electrode formed on the inner surface of the first and second transparent substrates, respectively; and a power supply and data signal distribution region surrounding at least a portion of the optically active display region and near the first and second scanners. The power supply and data signal distribution region comprises (a) a groove, and (b) a plurality of parallel conductors, formed on the inner surface of the second and first transparent substrates, respectively, which conductors include a height extending into the groove to reduce each conductor's resistance. Conductor capacitance is reduced by (a) eliminating the transparent common electrode from the groove, and/or (b) providing an inert dielectric material or gas in the distribution region with a lower dielectric constant than the liquid crystal material.

摘要翻译： 液晶显示装置具有密封在其间的液晶材料的第一和第二透明基板; 分别具有像素矩阵和第一和第二扫描仪的中心布置的光学活性显示区域和分别形成在第一和第二透明基板的内表面上的透明公共电极; 以及围绕光学活动显示区域的至少一部分并且靠近第一和第二扫描器的电源和数据信号分配区域。 电源和数据信号分配区域包括（a）分别形成在第二和第一透明基板的内表面上的凹槽和（b）多个平行导体，该导体包括延伸到凹槽中的高度 减少每个导线的电阻。 通过（a）从沟槽去除透明公共电极，和/或（b）在分布区域中提供比液晶材料低的介电常数的惰性电介质材料或气体来减小导体电容。