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公开(公告)号：US08765595B2
公开(公告)日：2014-07-01
申请号：US13345120
申请日：2012-01-06
IPC分类号： H01L21/4763
CPC分类号： H01L23/5227 , H01L21/76883 , H01L23/5283 , H01L23/5329 , H01L23/53295 , H01L28/10 , H01L2924/0002 , H01L2924/00
摘要： Methods for fabricating a back-end-of-line (BEOL) wiring structure, BEOL wiring structures, and design structures for a BEOL wiring structure. The BEOL wiring may be fabricated by forming a first wire in a dielectric layer and annealing the first wire in an oxygen-free atmosphere. After the first wire is annealed, a second wire is formed in vertical alignment with the first wire. A final passivation layer, which is comprised of an organic material such as polyimide, is formed that covers an entirety of a sidewall of the second wire.
摘要翻译： BEOL布线结构的制造方法，BEOL布线结构以及BEOL布线结构的设计结构。 BEOL布线可以通过在电介质层中形成第一布线并在无氧气氛中退火第一布线来制造。 在第一线退火之后，形成与第一线垂直对准的第二线。 形成由诸如聚酰亚胺的有机材料组成的最终钝化层，其覆盖第二线的整个侧壁。
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2.发明授权Integrated circuit including sensor structure, related method and design structure 有权集成电路包括传感器结构，相关方法和设计结构公开(公告)号：US08822993B2
公开(公告)日：2014-09-02
申请号：US13550813
申请日：2012-07-17
CPC分类号： H01L22/34 , G01R31/2858 , H01L22/30 , H01L23/48 , H01L2924/0002 , H01L2924/00
摘要： An Integrated Circuit (IC) and a method of making the same. In one embodiment, an integrated circuit includes: a substrate; a first metal layer disposed on the substrate and including a sensor structure configured to indicate a crack in a portion of the integrated circuit; and a second metal layer disposed proximate the first metal layer, the second metal layer including a wire component disposed proximate the sensor structure.
摘要翻译： 一种集成电路（IC）及其制造方法。 在一个实施例中，集成电路包括：基板; 第一金属层，设置在所述基板上并且包括被构造为指示所述集成电路的一部分中的裂纹的传感器结构; 以及设置在所述第一金属层附近的第二金属层，所述第二金属层包括靠近所述传感器结构设置的导线部件。
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3.发明申请INTEGRATED CIRCUIT INCLUDING SENSOR STRUCTURE, RELATED METHOD AND DESIGN STRUCTURE 有权集成电路，包括传感器结构，相关方法和设计结构公开(公告)号：US20140021469A1
公开(公告)日：2014-01-23
申请号：US13550813
申请日：2012-07-17
CPC分类号： H01L22/34 , G01R31/2858 , H01L22/30 , H01L23/48 , H01L2924/0002 , H01L2924/00
摘要： An Integrated Circuit (IC) and a method of making the same. In one embodiment, an integrated circuit includes: a substrate; a first metal layer disposed on the substrate and including a sensor structure configured to indicate a crack in a portion of the integrated circuit; and a second metal layer disposed proximate the first metal layer, the second metal layer including a wire component disposed proximate the sensor structure.
摘要翻译： 一种集成电路（IC）及其制造方法。 在一个实施例中，集成电路包括：基板; 第一金属层，设置在所述基板上并且包括被构造为指示所述集成电路的一部分中的裂纹的传感器结构; 以及设置在所述第一金属层附近的第二金属层，所述第二金属层包括靠近所述传感器结构设置的导线部件。
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公开(公告)号：US20130175073A1
公开(公告)日：2013-07-11
申请号：US13345120
申请日：2012-01-06
CPC分类号： H01L23/5227 , H01L21/76883 , H01L23/5283 , H01L23/5329 , H01L23/53295 , H01L28/10 , H01L2924/0002 , H01L2924/00
摘要： Methods for fabricating a back-end-of-line (BEOL) wiring structure, BEOL wiring structures, and design structures for a BEOL wiring structure. The BEOL wiring may be fabricated by forming a first wire in a dielectric layer and annealing the first wire in an oxygen-free atmosphere. After the first wire is annealed, a second wire is formed in vertical alignment with the first wire. A final passivation layer, which is comprised of an organic material such as polyimide, is formed that covers an entirety of a sidewall of the second wire.
摘要翻译： BEOL布线结构的制造方法，BEOL布线结构以及BEOL布线结构的设计结构。 BEOL布线可以通过在电介质层中形成第一布线并在无氧气氛中退火第一布线来制造。 在第一线退火之后，形成与第一线垂直对准的第二线。 形成由诸如聚酰亚胺的有机材料组成的最终钝化层，其覆盖第二线的整个侧壁。
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公开(公告)号：US20130133919A1
公开(公告)日：2013-05-30
申请号：US13304772
申请日：2011-11-28
申请人： Gregory S. Chrisman , Edward C. Cooney, III , Jeffrey P. Gambino , Zhong-Xiang He , Thomas L. McDevitt , Eva A. Shah
发明人： Gregory S. Chrisman , Edward C. Cooney, III , Jeffrey P. Gambino , Zhong-Xiang He , Thomas L. McDevitt , Eva A. Shah
CPC分类号： H01L23/562 , H01L21/7684 , H01L21/76883 , H01L23/5227 , H01L23/5283 , H01L2924/0002 , H01L2924/00
摘要： A structure and method for fabricating the structure that provides a metal wire having a first height at an upper surface. An insulating material surrounding said metal wire is etched to a second height below said first height of said upper surface. The metal wire from said upper surface, after etching said insulating material, is planarized to remove sufficient material from a lateral edge portion of said metal wire such that a height of said lateral edge portion is equivalent to said second height of said insulating material surrounding said metal wire.
摘要翻译： 一种用于制造提供在上表面具有第一高度的金属线的结构的结构和方法。 围绕所述金属线的绝缘材料被蚀刻到所述上表面的所述第一高度以下的第二高度。 在蚀刻所述绝缘材料之后，来自所述上表面的金属线被平坦化以从所述金属线的横向边缘部分去除足够的材料，使得所述侧边缘部分的高度等于围绕所述绝缘材料的所述绝缘材料的所述第二高度 金属丝。
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公开(公告)号：US08604618B2
公开(公告)日：2013-12-10
申请号：US13239533
申请日：2011-09-22
申请人： Edward C. Cooney, III , Jeffrey P. Gambino , Zhong-Xiang He , Xiao Hu Liu , Thomas L. McDevitt , Gary L. Milo , William J. Murphy
发明人： Edward C. Cooney, III , Jeffrey P. Gambino , Zhong-Xiang He , Xiao Hu Liu , Thomas L. McDevitt , Gary L. Milo , William J. Murphy
IPC分类号： H01L23/485 , H01L21/3205
CPC分类号： H01L21/76802 , H01L21/7682 , H01L23/5222 , H01L23/53295 , H01L23/562 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device and a method of fabricating the same, includes vertically stacked layers on an insulator. Each of the layers includes a first dielectric insulator portion, a first metal conductor embedded within the first dielectric insulator portion, a first nitride cap covering the first metal conductor, a second dielectric insulator portion, a second metal conductor embedded within the second dielectric insulator portion, and a second nitride cap covering the second metal conductor. The first and second metal conductors form first vertically stacked conductor layers and second vertically stacked conductor layers. The first vertically stacked conductor layers are proximate the second vertically stacked conductor layers, and at least one air gap is positioned between the first vertically stacked conductor layers and the second vertically stacked conductor layers. An upper semiconductor layer covers the first vertically stacked conductor layers, the air gap and the second plurality of vertically stacked conductor layers.
摘要翻译： 半导体器件及其制造方法包括在绝缘体上的垂直堆叠的层。 每个层包括第一介电绝缘体部分，嵌入在第一介电绝缘体部分内的第一金属导体，覆盖第一金属导体的第一氮化物帽，第二电介质绝缘体部分，嵌入在第二介电绝缘体部分内的第二金属导体 以及覆盖所述第二金属导体的第二氮化物帽。 第一和第二金属导体形成第一垂直堆叠的导体层和第二垂直堆叠的导体层。 第一垂直堆叠的导体层靠近第二垂直堆叠的导体层，并且至少一个气隙位于第一垂直堆叠的导体层和第二垂直堆叠的导体层之间。 上半导体层覆盖第一垂直堆叠的导体层，气隙和第二多个垂直堆叠的导体层。
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公开(公告)号：US20130075913A1
公开(公告)日：2013-03-28
申请号：US13239533
申请日：2011-09-22
申请人： Edward C. Cooney, III , Jeffrey P. Gambino , Zhong-Xiang He , Xiao Hu Liu , Thomas L. McDevitt , Gary L. Milo , William J. Murphy
发明人： Edward C. Cooney, III , Jeffrey P. Gambino , Zhong-Xiang He , Xiao Hu Liu , Thomas L. McDevitt , Gary L. Milo , William J. Murphy
IPC分类号： H01L23/485 , H01L21/3205
CPC分类号： H01L21/76802 , H01L21/7682 , H01L23/5222 , H01L23/53295 , H01L23/562 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device and a method of fabricating the same, includes vertically stacked layers on an insulator. Each of the layers includes a first dielectric insulator portion, a first metal conductor embedded within the first dielectric insulator portion, a first nitride cap covering the first metal conductor, a second dielectric insulator portion, a second metal conductor embedded within the second dielectric insulator portion, and a second nitride cap covering the second metal conductor. The first and second metal conductors form first vertically stacked conductor layers and second vertically stacked conductor layers. The first vertically stacked conductor layers are proximate the second vertically stacked conductor layers, and at least one air gap is positioned between the first vertically stacked conductor layers and the second vertically stacked conductor layers. An upper semiconductor layer covers the first vertically stacked conductor layers, the air gap and the second plurality of vertically stacked conductor layers.
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公开(公告)号：US09831122B2
公开(公告)日：2017-11-28
申请号：US13482864
申请日：2012-05-29
IPC分类号： H01L23/48 , H01L21/768 , H01L23/522 , H01L23/525 , H01L23/532 , H01L23/31 , H01L23/00
CPC分类号： H01L23/5226 , H01L21/76843 , H01L21/76879 , H01L21/76885 , H01L23/3114 , H01L23/3192 , H01L23/5227 , H01L23/525 , H01L23/53238 , H01L23/5329 , H01L24/03 , H01L24/05 , H01L2224/02166 , H01L2224/03462 , H01L2224/03831 , H01L2224/04042 , H01L2224/05567 , H01L2224/05624 , H01L2924/00014 , H01L2924/01029 , H01L2924/12042 , H01L2224/05552 , H01L2924/00
摘要： An integrated circuit (IC), design structure, and a method of making the same. In one embodiment, the IC includes: a substrate; a dielectric layer disposed on the substrate; a set of wire components disposed on the dielectric layer, the set of wire components including a first wire component disposed proximate a second wire component; a bond pad disposed on the first wire component, the bond pad including an exposed portion; a passivation layer disposed on the dielectric layer about a portion of the bond pad and the set of wire components, the passivation layer defining a wire structure via connected to the second wire component; and a wire structure disposed on the passivation layer proximate the bond pad and connected to the second wire component through the wire structure via.
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9.发明申请INTEGRATED CIRCUIT INCLUDING WIRE STRUCTURE, RELATED METHOD AND DESIGN STRUCTURE 有权集成电路，包括电线结构，相关方法和设计结构公开(公告)号：US20130320536A1
公开(公告)日：2013-12-05
申请号：US13482864
申请日：2012-05-29
IPC分类号： H01L23/52 , G06F17/50 , H01L21/768
CPC分类号： H01L23/5226 , H01L21/76843 , H01L21/76879 , H01L21/76885 , H01L23/3114 , H01L23/3192 , H01L23/5227 , H01L23/525 , H01L23/53238 , H01L23/5329 , H01L24/03 , H01L24/05 , H01L2224/02166 , H01L2224/03462 , H01L2224/03831 , H01L2224/04042 , H01L2224/05567 , H01L2224/05624 , H01L2924/00014 , H01L2924/01029 , H01L2924/12042 , H01L2224/05552 , H01L2924/00
摘要： An integrated circuit (IC), design structure, and a method of making the same. In one embodiment, the IC includes: a substrate; a dielectric layer disposed on the substrate; a set of wire components disposed on the dielectric layer, the set of wire components including a first wire component disposed proximate a second wire component; a bond pad disposed on the first wire component, the bond pad including an exposed portion; a passivation layer disposed on the dielectric layer about a portion of the bond pad and the set of wire components, the passivation layer defining a wire structure via connected to the second wire component; and a wire structure disposed on the passivation layer proximate the bond pad and connected to the second wire component through the wire structure via.
摘要翻译： 集成电路（IC），设计结构及其制作方法。 在一个实施例中，IC包括：衬底; 设置在所述基板上的电介质层; 设置在电介质层上的一组电线组件，该组电线组件包括靠近第二电线组件设置的第一电线组件; 设置在所述第一线材部件上的接合焊盘，所述接合焊盘包括暴露部分; 围绕所述接合焊盘和所述一组导线部件的一部分设置在所述电介质层上的钝化层，所述钝化层通过连接到所述第二导线部件限定线结构; 以及布线在靠近接合焊盘的钝化层上并通过导线结构通孔连接到第二导线部件的线结构。
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公开(公告)号：US08575022B2
公开(公告)日：2013-11-05
申请号：US13304772
申请日：2011-11-28
申请人： Gregory S. Chrisman , Edward C. Cooney, III , Jeffrey P. Gambino , Zhong-Xiang He , Thomas L. McDevitt , Eva A. Shah
发明人： Gregory S. Chrisman , Edward C. Cooney, III , Jeffrey P. Gambino , Zhong-Xiang He , Thomas L. McDevitt , Eva A. Shah
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L23/562 , H01L21/7684 , H01L21/76883 , H01L23/5227 , H01L23/5283 , H01L2924/0002 , H01L2924/00
摘要： A structure and method for fabricating the structure that provides a metal wire having a first height at an upper surface. An insulating material surrounding said metal wire is etched to a second height below said first height of said upper surface. The metal wire from said upper surface, after etching said insulating material, is planarized to remove sufficient material from a lateral edge portion of said metal wire such that a height of said lateral edge portion is equivalent to said second height of said insulating material surrounding said metal wire.
摘要翻译： 一种用于制造提供在上表面具有第一高度的金属线的结构的结构和方法。 围绕所述金属线的绝缘材料被蚀刻到所述上表面的所述第一高度以下的第二高度。 在蚀刻所述绝缘材料之后，来自所述上表面的金属线被平坦化以从所述金属线的横向边缘部分去除足够的材料，使得所述侧边缘部分的高度等于围绕所述绝缘材料的所述绝缘材料的所述第二高度 金属丝。
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