-
公开(公告)号：US09831122B2
公开(公告)日：2017-11-28
申请号：US13482864
申请日：2012-05-29
IPC分类号： H01L23/48 , H01L21/768 , H01L23/522 , H01L23/525 , H01L23/532 , H01L23/31 , H01L23/00
CPC分类号： H01L23/5226 , H01L21/76843 , H01L21/76879 , H01L21/76885 , H01L23/3114 , H01L23/3192 , H01L23/5227 , H01L23/525 , H01L23/53238 , H01L23/5329 , H01L24/03 , H01L24/05 , H01L2224/02166 , H01L2224/03462 , H01L2224/03831 , H01L2224/04042 , H01L2224/05567 , H01L2224/05624 , H01L2924/00014 , H01L2924/01029 , H01L2924/12042 , H01L2224/05552 , H01L2924/00
摘要： An integrated circuit (IC), design structure, and a method of making the same. In one embodiment, the IC includes: a substrate; a dielectric layer disposed on the substrate; a set of wire components disposed on the dielectric layer, the set of wire components including a first wire component disposed proximate a second wire component; a bond pad disposed on the first wire component, the bond pad including an exposed portion; a passivation layer disposed on the dielectric layer about a portion of the bond pad and the set of wire components, the passivation layer defining a wire structure via connected to the second wire component; and a wire structure disposed on the passivation layer proximate the bond pad and connected to the second wire component through the wire structure via.
-
2.发明申请INTEGRATED CIRCUIT INCLUDING WIRE STRUCTURE, RELATED METHOD AND DESIGN STRUCTURE 有权集成电路，包括电线结构，相关方法和设计结构公开(公告)号：US20130320536A1
公开(公告)日：2013-12-05
申请号：US13482864
申请日：2012-05-29
IPC分类号： H01L23/52 , G06F17/50 , H01L21/768
CPC分类号： H01L23/5226 , H01L21/76843 , H01L21/76879 , H01L21/76885 , H01L23/3114 , H01L23/3192 , H01L23/5227 , H01L23/525 , H01L23/53238 , H01L23/5329 , H01L24/03 , H01L24/05 , H01L2224/02166 , H01L2224/03462 , H01L2224/03831 , H01L2224/04042 , H01L2224/05567 , H01L2224/05624 , H01L2924/00014 , H01L2924/01029 , H01L2924/12042 , H01L2224/05552 , H01L2924/00
摘要： An integrated circuit (IC), design structure, and a method of making the same. In one embodiment, the IC includes: a substrate; a dielectric layer disposed on the substrate; a set of wire components disposed on the dielectric layer, the set of wire components including a first wire component disposed proximate a second wire component; a bond pad disposed on the first wire component, the bond pad including an exposed portion; a passivation layer disposed on the dielectric layer about a portion of the bond pad and the set of wire components, the passivation layer defining a wire structure via connected to the second wire component; and a wire structure disposed on the passivation layer proximate the bond pad and connected to the second wire component through the wire structure via.
摘要翻译： 集成电路（IC），设计结构及其制作方法。 在一个实施例中，IC包括：衬底; 设置在所述基板上的电介质层; 设置在电介质层上的一组电线组件，该组电线组件包括靠近第二电线组件设置的第一电线组件; 设置在所述第一线材部件上的接合焊盘，所述接合焊盘包括暴露部分; 围绕所述接合焊盘和所述一组导线部件的一部分设置在所述电介质层上的钝化层，所述钝化层通过连接到所述第二导线部件限定线结构; 以及布线在靠近接合焊盘的钝化层上并通过导线结构通孔连接到第二导线部件的线结构。
-
3.发明授权Methods for improved adhesion of protective layers of imager microlens structures by forming an interfacial region 有权通过形成界面区域来改善成像器微透镜结构的保护层的附着的方法公开(公告)号：US08476099B2
公开(公告)日：2013-07-02
申请号：US12841750
申请日：2010-07-22
申请人： Edward C. Cooney, III , Jeffrey P. Gambino , Robert K. Leidy , Charles F. Musante , John G. Twombly
发明人： Edward C. Cooney, III , Jeffrey P. Gambino , Robert K. Leidy , Charles F. Musante , John G. Twombly
IPC分类号： H01L21/473 , H01L31/18
CPC分类号： H01L31/02325 , C23C16/02 , C23C16/0272 , C23C16/402 , C23C16/505 , G06F17/5045 , H01L27/14627 , H01L27/14685
摘要： Methods, structures, and design structures for improved adhesion of protective layers of imager microlens structures are disclosed. A method of fabricating a semiconductor structure includes forming an interfacial region between a microlens and a protective oxide layer. The interfacial region has a lower concentration of oxygen than the protective oxide layer.
摘要翻译： 公开了用于改善成像器微透镜结构保护层附着力的方法，结构和设计结构。 制造半导体结构的方法包括在微透镜和保护氧化物层之间形成界面区域。 界面区域的氧浓度低于保护氧化物层。
-
公开(公告)号：US07781781B2
公开(公告)日：2010-08-24
申请号：US11560882
申请日：2006-11-17
申请人： James W. Adkisson , Jeffrey P. Gambino , Zhong-Xiang He , Mark D. Jaffe , Robert K. Leidy , Stephen E. Luce , Richard J. Rassel , Edmund J. Sprogis
发明人： James W. Adkisson , Jeffrey P. Gambino , Zhong-Xiang He , Mark D. Jaffe , Robert K. Leidy , Stephen E. Luce , Richard J. Rassel , Edmund J. Sprogis
IPC分类号： H01L27/15
CPC分类号： H01L27/14687 , H01L27/14618 , H01L27/14621 , H01L27/14627 , H01L27/14632 , H01L27/14685 , H01L2224/05001 , H01L2224/05008 , H01L2224/05124 , H01L2224/05548 , H01L2224/05569 , H01L2224/05647 , H01L2224/13 , H01L2924/00014
摘要： A CMOS image sensor array and method of fabrication. The CMOS imager sensor array comprises a substrate; an array of light receiving pixel structures formed above the substrate, the array having formed therein “m” levels of conductive structures, each level formed in a corresponding interlevel dielectric material layer; a dense logic wiring region formed adjacent to the array of light receiving pixel structures having “n” levels of conductive structures, each level formed in a corresponding interlevel dielectric material layer, where n>m. A microlens array having microlenses and color filters formed above the interlevel dielectric material layer, a microlens and respective color filter in alignment with a respective light receiving structure formed at a surface of the substrate. A top surface of the interlevel dielectric material layer beneath the microlens array is recessed from a top surface of the interlevel dielectric material layers of the dense logic wiring region.
摘要翻译： CMOS图像传感器阵列及其制造方法。 CMOS成像器传感器阵列包括衬底; 形成在衬底上方的光接收像素结构的阵列，阵列中形成有“m”级的导电结构，每个级形成在相应的层间介电材料层中; 与具有“n”级的导电结构的光接收像素结构的阵列相邻形成的密集的逻辑布线区域，每个层级形成在相应的层间电介质材料层中，其中n> m。 具有形成在层间电介质材料层上方的微透镜和滤色器的微透镜阵列，与形成在衬底表面处的各个光接收结构对准的微透镜和相应的滤色器。 微透镜阵列下面的层间介电材料层的顶表面从密集逻辑布线区域的层间介电材料层的顶表面凹陷。
-
公开(公告)号：US20080116537A1
公开(公告)日：2008-05-22
申请号：US11560882
申请日：2006-11-17
申请人： James W. Adkisson , Jeffrey P. Gambino , Zhong-Xiang He , Mark D. Jaffe , Robert K. Leidy , Stephen E. Luce , Richard J. Rassel , Edmund J. Sprogis
发明人： James W. Adkisson , Jeffrey P. Gambino , Zhong-Xiang He , Mark D. Jaffe , Robert K. Leidy , Stephen E. Luce , Richard J. Rassel , Edmund J. Sprogis
IPC分类号： H01L27/146 , H01L21/04
CPC分类号： H01L27/14687 , H01L27/14618 , H01L27/14621 , H01L27/14627 , H01L27/14632 , H01L27/14685 , H01L2224/05001 , H01L2224/05008 , H01L2224/05124 , H01L2224/05548 , H01L2224/05569 , H01L2224/05647 , H01L2224/13 , H01L2924/00014
摘要： A CMOS image sensor array and method of fabrication. The CMOS imager sensor array comprises a substrate; an array of light receiving pixel structures formed above the substrate, the array having formed therein “m” levels of conductive structures, each level formed in a corresponding interlevel dielectric material layer; a dense logic wiring region formed adjacent to the array of light receiving pixel structures having “n” levels of conductive structures, each level formed in a corresponding interlevel dielectric material layer, where n>m. A microlens array having microlenses and color filters formed above the interlevel dielectric material layer, a microlens and respective color filter in alignment with a respective light receiving structure formed at a surface of the substrate. A top surface of the interlevel dielectric material layer beneath the microlens array is recessed from a top surface of the interlevel dielectric material layers of the dense logic wiring region.
摘要翻译： CMOS图像传感器阵列及其制造方法。 CMOS成像器传感器阵列包括衬底; 形成在衬底上方的光接收像素结构的阵列，阵列中形成有“m”级的导电结构，每个级形成在相应的层间介电材料层中; 与具有“n”级的导电结构的光接收像素结构的阵列相邻形成的密集的逻辑布线区域，每个层级形成在相应的层间电介质材料层中，其中n> m。 具有形成在层间电介质材料层上方的微透镜和滤色器的微透镜阵列，与形成在衬底表面处的各个光接收结构对准的微透镜和相应的滤色器。 微透镜阵列下面的层间介电材料层的顶表面从密集逻辑布线区域的层间介电材料层的顶表面凹陷。
-
公开(公告)号：US08753917B2
公开(公告)日：2014-06-17
申请号：US12967625
申请日：2010-12-14
IPC分类号： H01L31/112
CPC分类号： H01L31/105 , H01L27/14632 , H01L27/14636 , H01L27/14665 , H01L27/14687
摘要： A design structure embodied in a machine readable medium used in a design process includes a first dielectric layer disposed on an intermediary layer, a first conductive pad portion and a first interconnect portion disposed on the first dielectric layer, a second dielectric layer disposed on the first dielectric layer, a first capping layer disposed on the first interconnect portion and a portion of the first conductive pad portion, a second capping layer disposed on the first capping layer and a portion of the second dielectric layer, an n-type doped silicon layer disposed on the second capping layer and the first conductive pad portion, an intrinsic silicon layer disposed on the n-type doped silicon layer, and a p-type doped silicon layer disposed on the intrinsic silicon layer.
摘要翻译： 体现在设计过程中使用的机器可读介质中的设计结构包括设置在中间层上的第一介电层，设置在第一介电层上的第一导电焊盘部分和第一互连部分，设置在第一介电层上的第二介电层 电介质层，设置在第一互连部分上的第一覆盖层和第一导电焊盘部分的一部分，设置在第一覆盖层上的第二封盖层和第二介电层的一部分，设置n型掺杂硅层 在第二覆盖层和第一导电焊盘部分上，设置在n型掺杂硅层上的本征硅层和设置在本征硅层上的p型掺杂硅层。
-
公开(公告)号：US20090302406A1
公开(公告)日：2009-12-10
申请号：US12132875
申请日：2008-06-04
CPC分类号： H01L27/14627 , H01L27/1463 , H01L27/14632 , H01L27/14636
摘要： A plurality of image sensor structures and a plurality of methods for fabricating the plurality of image sensor structures provide for inhibited cracking and delamination of a lens capping layer with respect to a planarizing layer within the plurality of image sensor structures. Particular image sensor structures and related methods include at least one dummy lens layer of different dimensions than active lens layer located over a circuitry portion of a substrate within the particular image sensor structures. Additional particular image sensor structures include at least one of an aperture within the planarizing layer and a sloped endwall of the planarizing layer located over a circuitry portion within the particular image sensor structures.
摘要翻译： 多个图像传感器结构和用于制造多个图像传感器结构的多种方法提供了相对于多个图像传感器结构内的平坦化层的透镜封盖层的抑制性破裂和分层。 特定的图像传感器结构和相关方法包括与位于特定图像传感器结构内的衬底的电路部分之上的有源透镜层不同的至少一个虚拟透镜层。 另外特定的图像传感器结构包括平坦化层内的孔径和位于特定图像传感器结构内的电路部分上方的平坦化层的倾斜端壁中的至少一个。
-
公开(公告)号：US20090124047A1
公开(公告)日：2009-05-14
申请号：US12353549
申请日：2009-01-14
申请人： James W. Adkisson , Jeffrey P. Gambino , Mark D. Jaffe , Robert K. Leidy , Stephen E. Luce , Richard J. Rassel , Edmund J. Sprogis
发明人： James W. Adkisson , Jeffrey P. Gambino , Mark D. Jaffe , Robert K. Leidy , Stephen E. Luce , Richard J. Rassel , Edmund J. Sprogis
IPC分类号： H01L21/70
CPC分类号： H01L27/14618 , H01L25/0657 , H01L2224/13025 , H01L2224/16145 , H01L2224/16146 , H01L2224/16227 , H01L2224/17181 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/13091 , H01L2924/15151 , H01L2924/00014 , H01L2924/00
摘要： An imaging system for use in a digital camera or cell phone utilizes one chip for logic and one chip for image processing. The chips are interconnected using around-the-edge or through via conductors extending from bond pads on the active surface of the imaging chip to backside metallurgy on the imaging chip. The backside metallurgy of the imaging chip is connected to metallurgy on the active surface of the logic chip using an array of solder bumps in BGA fashion. The interconnection arrangement provides a CSP which matches the space constraints of a cell phone, for example. The arrangement also utilizes minimal wire lengths for reduced noise. Connection of the CSP to a carrier package may be either by conductive through vias or wire bonding. The CSP is such that the imaging chip may readily be mounted across an aperture in the wall of a cell phone, for example, so as to expose the light sensitive pixels on the active surface of said imaging chip to light.
摘要翻译： 用于数码相机或手机的成像系统利用一个芯片用于逻辑和一个芯片用于图像处理。 这些芯片使用围绕成像芯片的有源表面上的接合焊盘的边缘或通孔导体互连，从而在成像芯片上进行背面冶金。 成像芯片的背面冶金采用BGA焊料凸块阵列与逻辑芯片的有源表面上的冶金连接。 互连装置提供例如与手机的空间限制相匹配的CSP。 该布置还利用最小的线长度来降低噪声。 将CSP连接到载体封装可以通过通孔或引线键合导电。 CSP使得成像芯片可以容易地安装在例如手机的壁中的孔之间，以便将所述成像芯片的有效表面上的光敏像素曝光到光。
-
公开(公告)号：US20080088014A1
公开(公告)日：2008-04-17
申请号：US11528227
申请日：2006-09-26
申请人： James W. Adkisson , Jeffrey P. Gambino , Mark D. Jaffe , Robert K. Leidy , Stephen E. Luce , Richard J. Rassel , Edmund J. Sprogis
发明人： James W. Adkisson , Jeffrey P. Gambino , Mark D. Jaffe , Robert K. Leidy , Stephen E. Luce , Richard J. Rassel , Edmund J. Sprogis
CPC分类号： H01L27/14618 , H01L25/0657 , H01L2224/13025 , H01L2224/16145 , H01L2224/16146 , H01L2224/16227 , H01L2224/17181 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/13091 , H01L2924/15151 , H01L2924/00014 , H01L2924/00
摘要： An imaging system for use in a digital camera or cell phone utilizes one chip for logic and one chip for image processing. The chips are interconnected using around-the-edge or through via conductors extending from bond pads on the active surface of the imaging chip to backside metallurgy on the imaging chip. The backside metallurgy of the imaging chip is connected to metallurgy on the active surface of the logic chip using an array of solder bumps in BGA fashion. The interconnection arrangement provides a CSP which matches the space constraints of a cell phone, for example. The arrangement also utilizes minimal wire lengths for reduced noise. Connection of the CSP to a carrier package may be either by conductive through vias or wire bonding. The CSP is such that the imaging chip may readily be mounted across an aperture in the wall of a cell phone, for example, so as to expose the light sensitive pixels on the active surface of said imaging chip to light.
摘要翻译： 用于数码相机或手机的成像系统利用一个芯片用于逻辑和一个芯片用于图像处理。 这些芯片使用围绕成像芯片的有源表面上的接合焊盘的边缘或通孔导体互连，从而在成像芯片上进行背面冶金。 成像芯片的背面冶金采用BGA焊料凸块阵列与逻辑芯片的有源表面上的冶金连接。 互连装置提供例如与手机的空间限制相匹配的CSP。 该布置还利用最小的线长度来降低噪声。 将CSP连接到载体封装可以通过通孔或引线键合导电。 CSP使得成像芯片可以容易地安装在例如手机的壁中的孔之间，以便将所述成像芯片的有效表面上的光敏像素曝光到光。
-
公开(公告)号：US07193289B2
公开(公告)日：2007-03-20
申请号：US10904807
申请日：2004-11-30
IPC分类号： H01L27/14
CPC分类号： H01L27/14685 , H01L21/76819 , H01L21/76834 , H01L21/76838 , H01L27/14621 , H01L27/14627 , H01L27/14636 , H01L27/14687
摘要： An image sensor array and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a thinner interlevel dielectric stack with improved thickness uniformity to result in a pixel array exhibiting increased light sensitivity. In the sensor array, each Cu metallization level includes a Cu metal wire structure formed at locations between each array pixel and, a barrier material layer is formed on top each Cu metal wire structure that traverses the pixel optical path. By implementing a single mask or self-aligned mask methodology, a single etch is conducted to completely remove the interlevel dielectric and barrier layers that traverse the optical path. The etched opening is then refilled with dielectric material. Prior to depositing the refill dielectric, a layer of either reflective or absorptive material is formed along the sidewalls of the etched opening to improve sensitivity of the pixels by either reflecting light to the underlying photodiode or by eliminating light reflections.
摘要翻译： 一种图像传感器阵列和制造方法，其中传感器包括铜（Cu）金属化水平，允许结合更薄的层间电介质叠层，改进的厚度均匀性，以产生呈现增加的光敏度的像素阵列。 在传感器阵列中，每个Cu金属化层包括在每个阵列像素之间的位置处形成的Cu金属线结构，并且阻挡材料层形成在穿过像素光路的每个Cu金属线结构上。 通过实现单掩模或自对准掩模方法，进行单次蚀刻以完全去除穿过光路的层间电介质层和阻挡层。 然后将蚀刻的开口用电介质材料重新填充。 在沉积再充填电介质之前，沿蚀刻开口的侧壁形成反射或吸收材料层，以通过将光反射到下面的光电二极管或通过消除光反射来提高像素的灵敏度。
-
-
-
-
-
-
-
-
-
搜索结果
96 条记录 (耗时 0.029 秒)
