Method for continuously measuring surface temperature of heated steel
strip
    2.
    发明授权
    Method for continuously measuring surface temperature of heated steel strip 失效
    连续测量加热钢带表面温度的方法

    公开(公告)号:US4553854A

    公开(公告)日:1985-11-19

    申请号:US558943

    申请日:1983-12-07

    CPC分类号: G01J5/52 G01J5/0022

    摘要: A method for continuously measuring the surface temperature of a heated steel strip, includes providing a flat reflecting plate so as to face a heated steel strip at an angle of inclination (.alpha.) with the steel strip. A radiation thermometer measures the amount of heat radiation energy which is emitted from an arbitrary point on the surface of the steel strip and comes directly into the radiation thermometer; and the thermometer also measures the total sum of heat radiation energy which (a) is emitted from a different point on the surface of the steel strip and comes into the radiation thermometer after having been reflected at least twice between the steel strip and the reflecting plate and, (b) is emitted from a final reflecting point, on the steel strip, of the heat radiation from said different point. The emissivity of the steel strip is computed on the basis of said total sum of the energies of the heat radiations and the amount of energy of the heat radiation from the arbitrary point; and the surface temperature of the steel strip is measured on the basis of the computed emissivity and the amount of energy of a reference heat radiation. The final angle of reflection (.theta.) from the steel strip of the heat radiation from said different point, and the angle of inclination (.alpha.) of the reflecting plate, are set at values which satisfy specific limits.

    摘要翻译: 一种用于连续测量加热钢带的表面温度的方法包括提供平板反射板,以便以与钢带倾斜角度(α)相对的方式面对加热的钢带。 辐射温度计测量从钢带表面上的任意点发射的热辐射能量,并直接进入辐射温度计; 并且温度计还测量(a)从钢带表面上的不同点发射并在钢带和反射板之间反射至少两次之后进入辐射温度计的总辐射能量的总和 并且(b)从所述不同点的热辐射从钢带上的最终反射点发射。 根据热辐射能量的总和和来自任意点的热辐射能量的量,计算钢带的发射率; 并根据计算的发射率和参考热辐射的能量来测量钢带的表面温度。 来自所述不同点的热辐射的钢带的最终反射角(θ)和反射板的倾斜角(α)被设定为满足特定极限的值。

    Semiconductor device and method for manufacturing same
    4.
    发明授权
    Semiconductor device and method for manufacturing same 有权
    半导体装置及其制造方法

    公开(公告)号:US07157322B2

    公开(公告)日:2007-01-02

    申请号:US09828862

    申请日:2001-04-10

    申请人: Kiyotaka Imai

    发明人: Kiyotaka Imai

    摘要: A semiconductor device including an NMOSFET which has an n-type source/drain main region containing arsenic and an n-type source/drain buffer region having arsenic and phosphorous of which a concentration is lower than that of the source/drain main region, and the concentration of the phosphorous in the source/drain buffer region is smaller than the concentration of the arsenic therein. The semiconductor device has a suppressed reverse short channel effect and reduced p-n junction leakage current. Further, the semiconductor device has a larger margin to a certain gate length and a specified threshold voltage to elevate a production yield.

    摘要翻译: 包括具有含有砷的n型源极/漏极主区域和具有浓度低于源极/漏极主区域的砷和磷的n型源极/漏极缓冲区域的NMOSFET的半导体器件,以及 源/漏缓冲区中的磷的浓度小于其中的砷的浓度。 半导体器件具有抑制的反向短沟道效应和降低的p-n结漏电流。 此外,半导体器件具有较大的裕度以达到一定的栅极长度和特定的阈值电压以提高产量。

    Method for manufacturing a semiconductor device having a silicide layer
    7.
    发明授权
    Method for manufacturing a semiconductor device having a silicide layer 失效
    具有硅化物层的半导体器件的制造方法

    公开(公告)号:US06489236B1

    公开(公告)日:2002-12-03

    申请号:US09692471

    申请日:2000-10-20

    IPC分类号: H01L2144

    摘要: A method for forming a MOSFET includes the steps of forming cobalt silicide layers on a polysilicon gate electrode and source/drain regions, implanting impurity ions to form source/drain extensions and diffusing the impurity ions in the source/drain extensions The temperature of the heat treatment for diffusing step is lower than the maximum of the temperatures of the heat treatment for forming the silicide layer, whereby a MOSFET having excellent short-channel characteristics and a higher reliability can be obtained.

    摘要翻译: 一种用于形成MOSFET的方法包括以下步骤:在多晶硅栅极电极和源极/漏极区域上形成钴硅化物层,注入杂质离子以形成源极/漏极延伸部分,并使杂质离子扩散到源极/漏极延伸部分中的温度 用于扩散步骤的处理低于用于形成硅化物层的热处理的温度的最大值,由此可以获得具有优异的短沟道特性和更高可靠性的MOSFET。

    SOI-MOS field effect transistor with improved source/drain structure and method of forming the same
    8.
    发明授权
    SOI-MOS field effect transistor with improved source/drain structure and method of forming the same 失效
    具有改善的源极/漏极结构的SOI-MOS场效应晶体管及其形成方法

    公开(公告)号:US06344675B1

    公开(公告)日:2002-02-05

    申请号:US09591506

    申请日:2000-06-12

    申请人: Kiyotaka Imai

    发明人: Kiyotaka Imai

    IPC分类号: H01L2900

    摘要: The present invention provides a source/drain structure formed in a semiconductor layer which has source and drain regions of a first conductivity type and a body portion of a second conductivity type disposed between said source and drain regions. The body portion is positioned under a gate insulation film over which a gate electrode is provided. The source region has a first low resistive region which is lower in electrical resistivity than said source region and said drain region having a second low resistive region which is lower in electrical resistively than said source region. For the first present invention, it is important that a distance of an inside edge portion of the first low resistive region from a first interface between the source region and the body portion is shorter than a distance of an inside portion of the second low resistive region from a second interface between the drain region and the body portion.

    摘要翻译: 本发明提供一种形成在半导体层中的源极/漏极结构,其具有设置在所述源极和漏极区域之间的第一导电类型的源区和漏极区以及第二导电类型的主体部分。 主体部分位于设置有栅电极的栅极绝缘膜的下方。 源区具有电阻率低于所述源极区的第一低电阻区域,而所述漏极区域具有电阻比所述源极区域低的第二低电阻区域。 对于第一本发明,重要的是,第一低电阻区域的内边缘部分与源区域和主体部分之间的第一界面的距离短于第二低电阻区域的内部部分的距离 从漏极区域和主体部分之间的第二界面。

    Method for fabricating a bipolar transistor with reduced base resistance
    9.
    发明授权
    Method for fabricating a bipolar transistor with reduced base resistance 失效
    具有降低的基极电阻的双极晶体管的制造方法

    公开(公告)号:US5424228A

    公开(公告)日:1995-06-13

    申请号:US258999

    申请日:1994-06-13

    申请人: Kiyotaka Imai

    发明人: Kiyotaka Imai

    CPC分类号: H01L29/66287

    摘要: A semiconductor device manufacturing method according to the present invention includes forming an outer base region in a collector layer. The outer base region connects an intrinsic base layer and a base electrode so that base contact resistance between them is decreased.

    摘要翻译: 根据本发明的半导体器件制造方法包括在集电体层中形成外部基极区域。 外部基极区域连接本征基极层和基极电极,使得它们之间的基极接触电阻降低。