Abstract:
Approaches for providing a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device are disclosed. A previously deposited amorphous carbon layer can be removed from over a mandrel that has been previously formed on a subset of a substrate, such as using a photoresist. A pad hardmask can be formed over the mandrel on the subset of the substrate. This formation results in the subset of the substrate having the pad hardmask covering the mandrel thereon and the remainder of the substrate having the amorphous carbon layer covering the mandrel thereon. This amorphous carbon layer can be removed from over the mandrel on the remainder of the substrate, allowing a set of fins to be formed therein while the amorphous carbon layer keeps the set of fins from being formed in the portion of the substrate that it covers.
Abstract:
Approaches for providing a substrate having a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device are disclosed. Specifically, the FinFET device comprises a finned substrate, and a planar metrology pad formed on the substrate adjacent the fins in a metrology measurement area of the FinFET device. Processing steps include forming a first hardmask over the substrate, forming a photoresist over a portion of the first hardmask in the metrology measurement area of the FinFET device, removing the first hardmask in an area adjacent the metrology measurement area remaining exposed following formation of the photoresist, patterning a set of openings in the substrate to form the set of fins in the FinFET device in the area adjacent the metrology measurement area, depositing an oxide layer over the FinFET device, and planarizing the FinFET device to form the planar metrology pad in the metrology measurement area.
Abstract:
Methods and systems are provided for fabricating and measuring physical features of a semiconductor device structure. An exemplary method of fabricating a semiconductor device structure involves obtaining a first measurement of a first attribute of the semiconductor device structure from a first metrology tool, obtaining process information pertaining to fabrication of one or more features of the semiconductor device structure by a first processing tool, and determining an adjusted measurement for the first attribute based at least in part on the first measurement in a manner that is influenced by the process information.
Abstract:
Various embodiments include computer-implemented methods, computer program products and systems for generating an integrated circuit (IC) library for use in a scatterometry analysis. In some cases, approaches include: obtaining chip design data about at least one IC chip; obtaining user input data about the at least one IC chip; and running an IC library defining program using the chip design data in its original format and the user input data in its original format, the running of the IC library defining program including: determining a process variation for the at least one IC chip based upon the chip design data and the user input data; converting the process variation into shape variation data; and providing the shape variation data in a text format to a scatterometry modeling program for use in the scatterometry analysis.
Abstract:
Methodologies and an apparatus for enabling three-dimensional scatterometry to be used to measure a thickness of dielectric layers in semiconductor devices are provided. Embodiments include initiating optical critical dimension (OCD) scatterometry on a three-dimensional test structure formed on a wafer, the three-dimensional test structure comprising patterned copper (Cu) trenches with an ultra-low k (ULK) dielectric film formed over the patterned Cu trenches; and obtaining, by a processor, a thickness of the ULK dielectric film based on results of the OCD scatterometry.
Abstract:
A computerized system and method are provided for use in measuring at least one parameter of interest of a structure. The system comprises a server utility configured for data communication with at least first and second data provider utilities. The server utility receives, from the server provider utilities, measured data comprising first and second measured data pieces of different types indicative of parameters of the same structure; and is capable of processing the first and second measured data pieces for optimizing one or more first parameters values of the structure in one of the first and second measured data pieces by utilizing one or more second parameters values of the structure of the other of said first and second measured data pieces.
Abstract:
Embodiments of the invention relate generally to semiconductor wafer technology and, more particularly, to the use of conformal grounding for active charge screening on wafers during wafer processing and metrology. A first aspect of the invention provides a method of reducing an accumulated surface charge on a semiconductor wafer, the method comprising: grounding a layer of conductive material adjacent a substrate of the wafer; and allowing a mirrored charge substantially equal in magnitude and opposite in sign to the accumulated surface charge to be induced along the conductive material.
Abstract:
Systems and methods for controlling manufacturing processes for microelectronic components are provided. In an exemplary embodiment, a method includes determining a specification range for a desired parameter. The microelectronic component is processed in a manufacturing tool, and a trace data set is recorded during the processing. An estimated trace data parameter is determined with the trace data set, and a first measured value of the microelectronic component is measured in a measurement tool. An estimated desired parameter is determined using the first measured value and the estimated trace data parameter, and the manufacturing process is adjusted when the estimated desired parameter is outside of the specification range.
Abstract:
Measurement of thickness of layers of a circuit structure is obtained, where the thickness of the layers is measured using an optical critical dimension (OCD) measurement technique, and the layers includes a high-k layer and an interfacial layer. Measurement of thickness of the high-k layer is separately obtained, where the thickness of the high-k layer is measured using a separate measurement technique from the OCD measurement technique. The separate measurement technique provides greater decoupling, as compared to the OCD measurement technique, of a signal for thickness of the high-k layer from a signal for thickness of the interfacial layer of the layers. Characteristics of the circuit structure, such as a thickness of the interfacial layer, are ascertained using, in part, the separately obtained thickness measurement of the high-k layer.
Abstract:
Approaches for providing a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device are disclosed. A previously deposited amorphous carbon layer can be removed from over a mandrel that has been previously formed on a subset of a substrate, such as using a photoresist. A pad hardmask can be formed over the mandrel on the subset of the substrate. This formation results in the subset of the substrate having the pad hardmask covering the mandrel thereon and the remainder of the substrate having the amorphous carbon layer covering the mandrel thereon. This amorphous carbon layer can be removed from over the mandrel on the remainder of the substrate, allowing a set of fins to be formed therein while the amorphous carbon layer keeps the set of fins from being formed in the portion of the substrate that it covers.