公开(公告)号：US20170012130A1

公开(公告)日：2017-01-12

申请号：US15273778

申请日：2016-09-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, Inc. ,  STMICROELECTRONICS, INC.

Inventor： Xiuyu CAI ,  Qing LIU ,  Ruilong XIE ,  Chun-Chen YEH

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/02 ,  H01L21/8234

Abstract: A large area electrical contact for use in integrated circuits features a non-planar, sloped bottom profile. The sloped bottom profile provides a larger electrical contact area, thus reducing the contact resistance, while maintaining a small contact footprint. The sloped bottom profile can be formed by recessing an underlying layer, wherein the bottom profile can be crafted to have a V-shape, U-shape, crescent shape, or other profile shape that includes at least a substantially sloped portion in the vertical direction. In one embodiment, the underlying layer is an epitaxial fin of a FinFET. A method of fabricating the low-resistance electrical contact employs a thin etch stop liner for use as a hard mask. The etch stop liner, e.g., HfO2, prevents erosion of an adjacent gate structure during the formation of the contact.

Abstract translation: 用于集成电路的大面积电接触具有非平面，倾斜的底部轮廓。 倾斜的底部轮廓提供更大的电接触面积，从而降低接触电阻，同时保持小的接触足迹。 倾斜的底部轮廓可以通过凹陷下面的层来形成，其中底部轮廓可以被制造成具有V形，U形，月牙形或其它轮廓形状，其在垂直方向上至少包括基本上倾斜的部分 。 在一个实施例中，下层是FinFET的外延翅片。 制造低电阻电接触的方法采用用作硬掩模的薄蚀刻停止衬垫。 蚀刻停止衬垫，例如HfO 2，防止在形成接触期间相邻栅极结构的侵蚀。

公开(公告)号：US20160190317A1

公开(公告)日：2016-06-30

申请号：US14587655

申请日：2014-12-31

Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing LIU ,  Ruilong XIE ,  Chun-chen YEH ,  Xiuyu CAI

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/165 ,  H01L29/40 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L29/7848 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/6681 ,  H01L29/7842 ,  H01L29/7851

Abstract: A hetero-channel FinFET device provides enhanced switching performance over a FinFET device having a silicon channel, and is easier to integrate into a fabrication process than is a FinFET device having a germanium channel. A FinFET device featuring the heterogeneous Si/SiGe channel includes a fin having a central region made of silicon and sidewall regions made of SiGe. A hetero-channel pFET device in particular has higher carrier mobility and less gate-induced drain leakage current than either a silicon device or a SiGe device. The hetero-channel FinFET permits the SiGe portion of the channel to have a Ge concentration in the range of about 25-40% and permits the fin height to exceed 40 nm while remaining stable.

Abstract translation: 异构沟道FinFET器件在具有硅沟道的FinFET器件上提供增强的开关性能，并且比具有锗通道的FinFET器件更容易集成到制造工艺中。 具有异质Si / SiGe沟道的FinFET器件包括具有由硅构成的中心区域和由SiGe制成的侧壁区域的翅片。 异质沟道pFET器件特别地具有比硅器件或SiGe器件更高的载流子迁移率和更小的栅极引起漏极漏电流。 异质沟道FinFET允许沟道的SiGe部分的Ge浓度在约25-40％的范围内，并且允许翅片高度超过40nm，同时保持稳定。

公开(公告)号：US20140110794A1

公开(公告)日：2014-04-24

申请号：US13654717

申请日：2012-10-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, INC.

Inventor： Ruilong XIE ,  Xiuyu CAI ,  Pranatharthiharan BALASUBRAMANIAN ,  Shom PONOTH

IPC: H01L21/283 ,  H01L29/423

CPC classification number: H01L29/66545 ,  H01L21/31053 ,  H01L21/76819 ,  H01L21/76837 ,  H01L21/76897 ,  H01L29/6653

Abstract: Methods of facilitating replacement gate processing and semiconductor devices formed from the methods are provided. The methods include, for instance, providing a plurality of sacrificial gate electrodes with sidewall spacers, the sacrificial gate electrodes with sidewall spacers being separated by, at least in part, a first dielectric material, wherein the first dielectric material is recessed below upper surfaces of the sacrificial gate electrodes, and the upper surfaces of the sacrificial gate electrodes are exposed and coplanar; conformally depositing a protective film over the sacrificial gate electrodes, the sidewall spacers, and the first dielectric material; providing a second dielectric material over the protective film, and planarizing the second dielectric material, stopping on and exposing the protective film over the sacrificial gate electrodes; and opening the protective film over the sacrificial gate electrodes to facilitate performing a replacement gate process.

Abstract translation: 提供了便于更换栅极处理的方法和由该方法形成的半导体器件。 所述方法包括例如提供具有侧壁间隔物的多个牺牲栅电极，具有侧壁间隔物的牺牲栅电极至少部分地由第一介电材料隔开，其中第一介电材料凹入下 牺牲栅电极和牺牲栅电极的上表面暴露并共面; 在牺牲栅电极，侧壁间隔物和第一介电材料上保形地沉积保护膜; 在所述保护膜上提供第二电介质材料，并且平坦化所述第二电介质材料，停止所述保护膜并在所述牺牲栅电极上暴露所述保护膜; 并且在牺牲栅电极之上打开保护膜以便于执行替换浇口工艺。

公开(公告)号：US20160190322A1

公开(公告)日：2016-06-30

申请号：US14584639

申请日：2014-12-29

Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, Inc.

Inventor： Qing LIU ,  Ruilong XIE ,  Xiuyu CAI ,  Chun-chen YEH

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/45 ,  H01L21/02 ,  H01L29/417 ,  H01L29/08

CPC classification number: H01L29/7851 ,  H01L21/02181 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823437 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795

Abstract: A large area electrical contact for use in integrated circuits features a non-planar, sloped bottom profile. The sloped bottom profile provides a larger electrical contact area, thus reducing the contact resistance, while maintaining a small contact footprint. The sloped bottom profile can be formed by recessing an underlying layer, wherein the bottom profile can be crafted to have a V-shape, U-shape, crescent shape, or other profile shape that includes at least a substantially sloped portion in the vertical direction. In one embodiment, the underlying layer is an epitaxial fin of a FinFET. A method of fabricating the low-resistance electrical contact employs a thin etch stop liner for use as a hard mask. The etch stop liner, e.g., HfO2, prevents erosion of an adjacent gate structure during the formation of the contact.

Abstract translation: 用于集成电路的大面积电接触具有非平面，倾斜的底部轮廓。 倾斜的底部轮廓提供更大的电接触面积，从而降低接触电阻，同时保持小的接触足迹。 倾斜的底部轮廓可以通过凹陷下面的层来形成，其中底部轮廓可以被制造成具有V形，U形，月牙形或其它轮廓形状，其在竖直方向上至少包括基本上倾斜的部分 。 在一个实施例中，下层是FinFET的外延翅片。 制造低电阻电接触的方法采用用作硬掩模的薄蚀刻停止衬垫。 蚀刻停止衬垫，例如HfO 2，防止在形成接触期间相邻栅极结构的侵蚀。

公开(公告)号：US20160181390A1

公开(公告)日：2016-06-23

申请号：US14581857

申请日：2014-12-23

Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing LIU ,  Xiuyu CAI ,  Chun-chen YEH ,  Ruilong XIE

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/45 ,  H01L29/417 ,  H01L29/51 ,  H01L21/311 ,  H01L29/78 ,  H01L29/40

CPC classification number: H01L29/45 ,  H01L21/76816 ,  H01L23/481 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/53266 ,  H01L23/535 ,  H01L23/5386 ,  H01L29/401 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: The present disclosure is directed to a device and method for reducing the resistance of the middle of the line in a transistor. The transistor has electrical contacts formed above, and electrically connected to, the gate, drain and source. The electrical contact connected to the gate includes a tungsten contact member deposited over the gate, and a copper contact deposited over the tungsten contact member. The electrical contacts connected to the drain and source include tungsten portions deposited over the drain and source regions, and copper contacts deposited over the tungsten portions.

Abstract translation: 本公开涉及一种用于降低晶体管中线的电阻的装置和方法。 晶体管具有形成在栅极，漏极和源极上方并电连接的电触点。 连接到栅极的电触点包括沉积在栅极上的钨接触构件和沉积在钨接触构件上的铜触点。 连接到漏极和源极的电触头包括沉积在漏极和源极区域上的钨部分，以及沉积在钨部分上的铜触点。

公开(公告)号：US20160141489A1

公开(公告)日：2016-05-19

申请号：US14841997

申请日：2015-09-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan ZHANG ,  Ruilong XIE ,  Xiuyu CAI ,  Seowoo NAM ,  Hyun-Jin CHO

IPC: H01L43/08 ,  H01L43/12 ,  H01L43/02

CPC classification number: H01L43/08 ,  G11C11/161 ,  H01L21/02 ,  H01L27/222 ,  H01L27/226 ,  H01L27/228 ,  H01L43/02 ,  H01L43/12

Abstract: A method of forming a self-aligned MTJ without using a photolithography mask and the resulting device are provided. Embodiments include forming a first electrode over a metal layer, the metal layer recessed in a low-k dielectric layer; forming a MTJ layer over the first electrode; forming a second electrode over the MTJ layer; removing portions of the second electrode, the MTJ layer, and the first electrode down to the low-k dielectric layer; forming a silicon nitride-based layer over the second electrode and the low-k dielectric layer; and planarizing the silicon nitride-based layer down to the second electrode.

Abstract translation: 提供了不使用光刻掩模形成自对准MTJ的方法和所得到的器件。 实施例包括在金属层上形成第一电极，金属层凹入低k电介质层中; 在第一电极上形成MTJ层; 在MTJ层上形成第二电极; 将所述第二电极，所述MTJ层和所述第一电极的部分去除到所述低k电介质层; 在所述第二电极和所述低k电介质层上形成氮化硅基层; 并将氮化硅基层平坦化到第二电极。

公开(公告)号：US20150357439A1

公开(公告)日：2015-12-10

申请号：US14295618

申请日：2014-06-04

Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing LIU ,  Ruilong XIE ,  Xiuyu CAI ,  Chun-chen YEH

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/762 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/76224 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/6681 ,  H01L29/785

Abstract: A method for making a semiconductor device may include forming, above a substrate, a plurality of laterally spaced-apart semiconductor fins, and forming regions of a first dielectric material between the laterally spaced-apart semiconductor fins. The method may further include selectively removing at least one intermediate semiconductor fin from among the plurality of semiconductor fins to define at least one trench between corresponding regions of the first dielectric material, and forming a region of a second dielectric material different than the first dielectric in the at least one trench to provide at least one isolation pillar between adjacent semiconductor fins.

Abstract translation: 制造半导体器件的方法可以包括在衬底之上形成多个横向间隔开的半导体鳍片，以及在横向间隔开的半导体鳍片之间形成第一电介质材料的区域。 该方法还可以包括：从多个半导体鳍片中选择性地移除至少一个中间半导体鳍片，以限定第一介电材料的相应区域之间的至少一个沟槽，以及形成与第一电介质不同的第二电介质材料的区域 所述至少一个沟槽用于在相邻的半导体鳍片之间提供至少一个隔离柱。

公开(公告)号：US20150348787A1

公开(公告)日：2015-12-03

申请号：US14288551

申请日：2014-05-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xiuyu CAI

IPC: H01L21/28 ,  H01L21/3213 ,  H01L21/321 ,  H01L29/49 ,  H01L29/66 ,  H01L21/027

CPC classification number: H01L21/28035 ,  H01L21/0332 ,  H01L21/28123 ,  H01L21/31122 ,  H01L21/32139 ,  H01L29/4916

Abstract: A method for forming a gate of a semiconductor device includes providing a semiconductor substrate, forming an active region with trench isolation in the semiconductor substrate, providing a polysilicon layer disposed on the semiconductor substrate, and providing a hard mask layer disposed on the polysilicon layer. An ash resistant layer is disposed on the hard mask layer. Patterned portions of the ash resistant layer, the hard mask, and the polysilicon layer are moved, and the remaining portions of the ash resistant layer is wherein the patterned polysilicon layer defines the gate. The resistant layer inhibits or reduces the likelihood of pitting of the polysilicon layer and substrate during subsequent etching processes.

Abstract translation: 一种用于形成半导体器件的栅极的方法包括提供半导体衬底，在半导体衬底中形成具有沟槽隔离的有源区，提供设置在半导体衬底上的多晶硅层，以及提供设置在多晶硅层上的硬掩模层。 防硬层设置在硬掩模层上。 防灰层，硬掩模和多晶硅层的图案部分被移动，并且耐灰层的其余部分是其中图案化多晶硅层限定栅极。 耐蚀层在随后的蚀刻工艺期间抑制或降低多晶硅层和衬底的点蚀的可能性。

公开(公告)号：US20150228781A1

公开(公告)日：2015-08-13

申请号：US14175215

申请日：2014-02-07

Applicant: GLOBALFOUNDRIES Inc. ,  STMICROELECTRONICS, INC.

Inventor： Xiuyu CAI ,  Qing LlU ,  Ruilong XIE

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848

Abstract: A method is for making a semiconductor device. The method may include forming fins above a substrate, each fin having an upper fin portion including a first semiconductor material and a lower fin portion including a dielectric material. The method may include forming recesses into sidewalls of each lower fin portion to expose a lower surface of a respective upper fin portion, and forming a second semiconductor layer surrounding the fins including the exposed lower surfaces of the upper fin portions. The second semiconductor layer may include a second semiconductor material to generate stress in the first semiconductor material.

Abstract translation: 一种制造半导体器件的方法。 该方法可以包括在基板上形成翅片，每个翅片具有包括第一半导体材料的上翅片部分和包括电介质材料的下翅片部分。 该方法可以包括在每个下部翅片部分的侧壁中形成凹部以暴露相应的上部翅片部分的下表面，以及形成包围上翅片部分暴露的下表面的翅片的第二半导体层。 第二半导体层可以包括在第一半导体材料中产生应力的第二半导体材料。

公开(公告)号：US20150349085A1

公开(公告)日：2015-12-03

申请号：US14288766

申请日：2014-05-28

Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing LIU ,  Ruilong XIE ,  Xiuyu CAI ,  Chun-chen YEH

IPC: H01L29/66 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/0228 ,  H01L21/31105 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/785 ,  H01L29/7851

Abstract: A method for making a semiconductor device includes forming laterally spaced-apart semiconductor fins above a substrate. At least one dielectric layer is formed adjacent an end portion of the semiconductor fins and within the space between adjacent semiconductor fins. A pair of sidewall spacers is formed adjacent outermost semiconductor fins at the end portion of the semiconductor fins. The at least one dielectric layer and end portion of the semiconductor fins between the pair of sidewall spacers are removed. Source/drain regions are formed between the pair of sidewall spacers.

Abstract translation: 制造半导体器件的方法包括在衬底上形成横向间隔开的半导体鳍片。 在半导体鳍片的端部附近和相邻的半导体鳍片之间的空间内形成至少一个电介质层。 在半导体翅片的端部处邻近最外半导体翅片形成一对侧壁间隔物。 去除该对侧壁间隔物之间​​的至少一个电介质层和半导体翅片的端部。 源极/漏极区域形成在该对侧壁间隔物之间​​。