公开(公告)号：US20160141242A1

公开(公告)日：2016-05-19

申请号：US15001390

申请日：2016-01-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ryan Kim ,  Jason R. Cantone ,  Wenhui Wang

IPC: H01L23/528 ,  H01L27/11 ,  H01L23/522

CPC classification number: H01L23/528 ,  H01L21/743 ,  H01L21/76816 ,  H01L21/76897 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/5226 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A methodology for forming contact areas by a multiple patterning process that provides increased yield and lower risk of contact-to-contact short at points of tight tip-to-tip spacing and the resulting device are disclosed. Embodiments include forming one or more trench patterning layers on a planarized surface of a wafer, forming one or more trenches in the one or more trench patterning layers, forming a block mask at one or more points along the one or more trenches, extending the one or more trenches down to a substrate level of the wafer, and removing the block mask from the one or more points.

Abstract translation: 公开了一种用于通过多重图案化工艺形成接触面积的方法，其提供增加的产量并且在紧密的尖端到尖端间距的点处产生接触 - 接触短的风险以及所得到的装置。 实施例包括在晶片的平坦化表面上形成一个或多个沟槽图案化层，在一个或多个沟槽图案化层中形成一个或多个沟槽，在沿一个或多个沟槽的一个或多个点处形成阻挡掩模， 或更多的沟槽直到晶片的衬底水平，以及从一个或多个点移除阻挡掩模。

公开(公告)号：US09275889B2

公开(公告)日：2016-03-01

申请号：US14045340

申请日：2013-10-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ryan Kim ,  Jason R. Cantone ,  Wenhui Wang

IPC: H01L21/4763 ,  H01L21/74 ,  H01L27/11 ,  H01L21/8234 ,  H01L27/02

CPC classification number: H01L23/528 ,  H01L21/743 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/5226 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A methodology for forming contact areas by a multiple patterning process that provides increased yield and lower risk of contact-to-contact short at points of tight tip-to-tip spacing and the resulting device are disclosed. Embodiments include forming one or more trench patterning layers on a planarized surface of a wafer, forming one or more trenches in the one or more trench patterning layers, forming a block mask at one or more points along the one or more trenches, extending the one or more trenches down to a substrate level of the wafer, and removing the block mask from the one or more points.

Abstract translation: 公开了一种用于通过多重图案化工艺形成接触面积的方法，其提供增加的产量并且在紧密的尖端到尖端间距的点处产生接触 - 接触短的风险以及所得到的装置。 实施例包括在晶片的平坦化表面上形成一个或多个沟槽图案化层，在一个或多个沟槽图案化层中形成一个或多个沟槽，在沿一个或多个沟槽的一个或多个点处形成阻挡掩模， 或更多的沟槽直到晶片的衬底水平，以及从一个或多个点移除阻挡掩模。

公开(公告)号：US20150129934A1

公开(公告)日：2015-05-14

申请号：US14079159

申请日：2013-11-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Vimal K. Kamineni ,  Abner F. Bello ,  Nicholas V. LiCausi ,  Wenhui Wang ,  Michael Wedlake ,  Jason R. Cantone

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/165 ,  H01L21/8234

CPC classification number: H01L29/785 ,  H01L21/02164 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/308 ,  H01L21/32133 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7843 ,  H01L29/7846 ,  H01L2029/7858

Abstract: One method disclosed includes performing a selective etching process through a gate cavity to selectively remove a portion of a first semiconductor material relative to a second layer of a second semiconductor material and a substrate so as to thereby define a space between the second semiconducting material and the substrate, filling substantially all of the space with an insulating material so as to thereby define a substantially self-aligned channel isolation region positioned under at least what will become the channel region of the FinFET device.

Abstract translation: 所公开的一种方法包括通过栅极腔执行选择性蚀刻工艺，以相对于第二半导体材料和衬底的第二层选择性地去除第一半导体材料的一部分，从而限定第二半导体材料与第二半导体材料之间的空间 衬底，用绝缘材料填充基本上所有的空间，从而限定位于至少将成为FinFET器件的沟道区的至少自对准沟道隔离区。

公开(公告)号：US08790522B1

公开(公告)日：2014-07-29

申请号：US13764051

申请日：2013-02-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Gerard M. Schmid ,  Richad A. Farrell ,  Ji Xu ,  Jason R. Cantone ,  Moshe E. Preil

IPC: H01B13/00

CPC classification number: B44C1/227 ,  H01L21/0337

Abstract: A method includes forming a chemical guide layer above a process layer. A template having a plurality of elements is formed above the process layer. The chemical guide layer is disposed on at least portions of the process layer disposed between adjacent elements of the template. A directed self-assembly layer is formed over the chemical guide layer. The directed self-assembly layer has alternating etchable components and etch-resistant components. The etchable components of the directed self-assembly layer are removed. The process layer is patterned using the template and the etch-resistant components of the directed self-assembly layer as an etch mask.

Abstract translation: 一种方法包括在处理层之上形成化学引导层。 具有多个元件的模板形成在处理层的上方。 化学引导层设置在设置在模板的相邻元件之间的处理层的至少一部分上。 导向的自组装层形成在化学引导层上。 定向自组装层具有交替的可蚀刻部件和耐蚀刻部件。 去除了定向自组装层的可蚀刻部件。 使用模板和定向自组装层的耐蚀刻部件作为蚀刻掩模对工艺层进行图案化。

公开(公告)号：US20140154630A1

公开(公告)日：2014-06-05

申请号：US13693627

申请日：2012-12-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Gerard M. Schmid ,  Richad A. Farrell ,  Ji Xu ,  Jason R. Cantone ,  Moshe E. Preil

IPC: G03F7/20

CPC classification number: G03F7/0002

Abstract: A method includes forming a template having a plurality of elements above a process layer, wherein portions of the process layer are exposed between adjacent elements of the template. A directed self-assembly layer is formed over the exposed portions. The directed self-assembly layer has alternating etchable components and etch-resistant components. The etchable components of the directed self-assembly layer are removed. The process layer is patterned using the template and the etch-resistant components of the directed self-assembly layer. Non-periodic elements are defined in the process later by the template and periodic elements are defined in the process layer by the etch-resistant components of the directed self-assembly layer.

Abstract translation: 一种方法包括在处理层之上形成具有多个元素的模板，其中处理层的部分在模板的相邻元素之间露出。 在暴露部分上形成定向的自组装层。 定向自组装层具有交替的可蚀刻部件和耐蚀刻部件。 去除了定向自组装层的可蚀刻部件。 使用模板和定向自组装层的耐蚀刻部件对工艺层进行图案化。 非周期元素在该过程中由模板定义，并且周期元素由定向自组装层的耐蚀刻部件在工艺层中定义。

公开(公告)号：US09093302B2

公开(公告)日：2015-07-28

申请号：US14079159

申请日：2013-11-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Vimal K. Kamineni ,  Abner F. Bello ,  Nicholas V. LiCausi ,  Wenhui Wang ,  Michael Wedlake ,  Jason R. Cantone

IPC: H01L21/84 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/12 ,  H01L27/108 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/165

CPC classification number: H01L29/785 ,  H01L21/02164 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/308 ,  H01L21/32133 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7843 ,  H01L29/7846 ,  H01L2029/7858

Abstract: One method disclosed includes performing a selective etching process through a gate cavity to selectively remove a portion of a first semiconductor material relative to a second layer of a second semiconductor material and a substrate so as to thereby define a space between the second semiconducting material and the substrate, filling substantially all of the space with an insulating material so as to thereby define a substantially self-aligned channel isolation region positioned under at least what will become the channel region of the FinFET device.

Abstract translation: 所公开的一种方法包括通过栅极腔执行选择性蚀刻工艺，以相对于第二半导体材料和衬底的第二层选择性地去除第一半导体材料的一部分，从而限定第二半导体材料与第二半导体材料之间的空间 衬底，用绝缘材料填充基本上所有的空间，从而限定位于至少将成为FinFET器件的沟道区的至少自对准沟道隔离区。

公开(公告)号：US08956808B2

公开(公告)日：2015-02-17

申请号：US13693627

申请日：2012-12-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Gerard M. Schmid ,  Richad A. Farrell ,  Ji Xu ,  Jason R. Cantone ,  Moshe E. Preil

IPC: G03F7/26 ,  G03F7/20

CPC classification number: G03F7/0002

Abstract: A method includes forming a template having a plurality of elements above a process layer, wherein portions of the process layer are exposed between adjacent elements of the template. A directed self-assembly layer is formed over the exposed portions. The directed self-assembly layer has alternating etchable components and etch-resistant components. The etchable components of the directed self-assembly layer are removed. The process layer is patterned using the template and the etch-resistant components of the directed self-assembly layer. Non-periodic elements are defined in the process later by the template and periodic elements are defined in the process layer by the etch-resistant components of the directed self-assembly layer.

Abstract translation: 一种方法包括在处理层之上形成具有多个元素的模板，其中处理层的部分在模板的相邻元素之间露出。 在暴露部分上形成定向的自组装层。 定向自组装层具有交替的可蚀刻部件和耐蚀刻部件。 去除了定向自组装层的可蚀刻部件。 使用模板和定向自组装层的耐蚀刻部件对工艺层进行图案化。 非周期元素在该过程中由模板定义，并且周期元素由定向自组装层的耐蚀刻部件在工艺层中定义。

公开(公告)号：US20140224764A1

公开(公告)日：2014-08-14

申请号：US13764051

申请日：2013-02-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Gerard M. Schmid ,  Richad A. Farrell ,  Ji Xu ,  Jason R. Cantone ,  Moshe E. Preil

IPC: B44C1/22

CPC classification number: B44C1/227 ,  H01L21/0337

Abstract: A method includes forming a chemical guide layer above a process layer. A template having a plurality of elements is formed above the process layer. The chemical guide layer is disposed on at least portions of the process layer disposed between adjacent elements of the template. A directed self-assembly layer is formed over the chemical guide layer. The directed self-assembly layer has alternating etchable components and etch-resistant components. The etchable components of the directed self-assembly layer are removed. The process layer is patterned using the template and the etch-resistant components of the directed self-assembly layer as an etch mask.

Abstract translation: 一种方法包括在处理层之上形成化学引导层。 具有多个元件的模板形成在处理层的上方。 化学引导层设置在设置在模板的相邻元件之间的处理层的至少一部分上。 导向的自组装层形成在化学引导层上。 定向自组装层具有交替的可蚀刻部件和耐蚀刻部件。 去除了定向自组装层的可蚀刻部件。 使用模板和定向自组装层的耐蚀刻部件作为蚀刻掩模对工艺层进行图案化。

公开(公告)号：US20160190306A1

公开(公告)日：2016-06-30

申请号：US15063633

申请日：2016-03-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Vimal K. Kamineni ,  Abner F. Bello ,  Nicholas V. LiCausi ,  Wenhui Wang ,  Michael Wedlake ,  Jason R. Cantone

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/51 ,  H01L29/06

CPC classification number: H01L21/823431 ,  H01L21/02164 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/308 ,  H01L21/32133 ,  H01L21/76224 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/785 ,  H01L2029/7858

Abstract: One illustrative device disclosed herein includes, among other things, a semiconductor substrate, a fin structure, a gate structure positioned around a portion of the fin structure in the channel region of the device, spaced-apart portions of a second semiconductor material positioned vertically between the fin structure and the substrate, wherein the second semiconductor material is a different semiconductor material than that of the fin, and a local channel isolation material positioned laterally between the spaced-apart portions of the second semiconductor material and vertically below the fin structure and the gate structure, wherein the local channel isolation material is positioned under at least a portion of the channel region of the device.

Abstract translation: 本文公开的一个说明性装置尤其包括半导体衬底，翅片结构，位于器件的沟道区域中的翅片结构的一部分周围的栅极结构，第二半导体材料的间隔开的部分位于 所述翅片结构和所述基板，其中所述第二半导体材料是与所述翅片不同的半导体材料，以及局部通道隔离材料，其横向位于所述第二半导体材料的所述间隔开的部分之间并且垂直于所述翅片结构的下方， 栅极结构，其中所述局部沟道隔离材料位于所述器件的沟道区域的至少一部分的下方。

公开(公告)号：US09318388B2

公开(公告)日：2016-04-19

申请号：US14725663

申请日：2015-05-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Vimal K. Kamineni ,  Abner F. Bello ,  Nicholas V. LiCausi ,  Wenhui Wang ,  Michael Wedlake ,  Jason R. Cantone

IPC: H01L21/84 ,  H01L21/8238 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/165 ,  H01L29/66 ,  H01L27/092 ,  H01L27/12 ,  H01L27/108 ,  H01L21/02 ,  H01L21/308 ,  H01L21/3213 ,  H01L21/762 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L21/02164 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/308 ,  H01L21/32133 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7843 ,  H01L29/7846 ,  H01L2029/7858

Abstract: One method disclosed includes performing a selective etching process through a gate cavity to selectively remove a portion of a first semiconductor material relative to a second layer of a second semiconductor material and a substrate so as to thereby define a space between the second semiconducting material and the substrate, filling substantially all of the space with an insulating material so as to thereby define a substantially self-aligned channel isolation region positioned under at least what will become the channel region of the FinFET device.