公开(公告)号：US20180158745A1

公开(公告)日：2018-06-07

申请号：US15367888

申请日：2016-12-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Dirk Breuer ,  Maik Liebau ,  Matthias Lehr

IPC: H01L23/26 ,  H01L23/31 ,  H01L23/522 ,  H01L23/528 ,  H01L21/56 ,  H01L21/66 ,  H01L21/768

CPC classification number: H01L23/26 ,  H01L21/56 ,  H01L21/76898 ,  H01L22/12 ,  H01L23/3107 ,  H01L23/3142 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/562 ,  H01L2224/4903 ,  H01L2224/94

Abstract: The patterning technique used for forming sophisticated metallization systems of semiconductor devices may be monitored and evaluated more efficiently by incorporating at least one via line feature into the die seal. In this manner, high statistical significance may be obtained compared to conventional strategies, in which the respective test structures for evaluating patterning processes may be provided at specific sites in the frame region and/or die region. Moreover, by providing a “long” via line feature, superior sensitivity for variations of depth of focus may be achieved.

公开(公告)号：US09324631B2

公开(公告)日：2016-04-26

申请号：US13870411

申请日：2013-04-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Axel Walter ,  Matthias Lehr

IPC: H01L23/58 ,  H01L23/48 ,  H01L23/528 ,  H01L23/532 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/552

CPC classification number: H01L23/481 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/3677 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/552 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L2224/03 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05022 ,  H01L2224/05147 ,  H01L2224/05541 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/0558 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/06133 ,  H01L2224/1148 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/81191 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A bump structure or pillar structure formed above a metallization system of a complex semiconductor device may include a stress buffer layer, which may efficiently distribute the resulting mechanical stress which may typically occur during the chip package interaction due to a thermal mismatch of these components. The stress buffer layer comprises copper-based buffer regions that cover a significant portion of the overall surface, wherein a thickness of approximately 3-10 μm may also be used. Moreover, the buffer regions may efficiently replace aluminum as a terminal metal active region.

Abstract translation: 形成在复合半导体器件的金属化系统之上的凸起结构或柱结构可以包括应力缓冲层，其可以有效地分布由于这些部件的热失配而在芯片封装相互作用期间通常发生的所得到的机械应力。 应力缓冲层包括覆盖整个表面的重要部分的铜基缓冲区，其中也可以使用约3-10μm的厚度。 此外，缓冲区域可以有效地代替铝作为末端金属活性区域。

公开(公告)号：US20180286773A1

公开(公告)日：2018-10-04

申请号：US15996960

申请日：2018-06-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Dirk Breuer ,  Maik Liebau ,  Matthias Lehr

IPC: H01L23/26 ,  H01L23/00 ,  H01L23/31 ,  H01L21/768 ,  H01L21/56 ,  H01L23/528 ,  H01L23/522 ,  H01L21/66

Abstract: A semiconductor device includes a metallization system positioned above a substrate and a die seal positioned at least in the metallization system and delimiting a die region. The die seal includes a via line feature having an axial length and including one or more first portions having a first target dimension and one or more second portions along the axial length. The one or more second portions have a second target dimension less than the first target dimension.

公开(公告)号：US09136234B2

公开(公告)日：2015-09-15

申请号：US13937361

申请日：2013-07-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Matthias Lehr ,  Marcel Wieland ,  Martin O'Toole

IPC: H01L23/48 ,  H01L23/00

CPC classification number: H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/13021 ,  H01L2224/1308 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/351 ,  H01L2924/01202 ,  H01L2924/00

Abstract: When forming sophisticated semiconductor devices including metal pillars arranged on contact pads, which may comprise aluminum, device performance and reliability may be improved by avoiding exposure of the contact pad material to the ambient atmosphere, in particular during and between dicing and packaging processes. To this end, the contact pad material may be covered by a protection layer or may be protected by the metal pillars itself, thereby concurrently improving mechanical stress distribution in the device.

Abstract translation: 当形成复杂的半导体器件时，包括布置在可包括铝的接触焊盘上的金属柱，可以通过避免将接触垫材料暴露于环境大气中，特别是在切割和封装过程期间以及在切割和包装过程之间，从而提高器件的性能和可靠性。 为此，接触垫材料可以被保护层覆盖，或者可以被金属支柱本身保护，从而同时改善装置中的机械应力分布。

公开(公告)号：US20150014843A1

公开(公告)日：2015-01-15

申请号：US13937361

申请日：2013-07-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Matthias Lehr ,  Marcel Wieland ,  Martin O'Toole

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/13021 ,  H01L2224/1308 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/351 ,  H01L2924/01202 ,  H01L2924/00

Abstract: When forming sophisticated semiconductor devices including metal pillars arranged on contact pads, which may comprise aluminum, device performance and reliability may be improved by avoiding exposure of the contact pad material to the ambient atmosphere, in particular during and between dicing and packaging processes. To this end, the contact pad material may be covered by a protection layer or may be protected by the metal pillars itself, thereby concurrently improving mechanical stress distribution in the device.

Abstract translation: 当形成复杂的半导体器件时，包括布置在可包括铝的接触焊盘上的金属柱，可以通过避免将接触垫材料暴露于环境大气中，特别是在切割和封装过程期间以及在切割和包装过程之间，从而提高器件的性能和可靠性。 为此，接触垫材料可以被保护层覆盖，或者可以被金属支柱本身保护，从而同时改善装置中的机械应力分布。

公开(公告)号：US10607947B2

公开(公告)日：2020-03-31

申请号：US15996960

申请日：2018-06-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Dirk Breuer ,  Maik Liebau ,  Matthias Lehr

IPC: H01L23/00 ,  H01L21/66 ,  H01L23/31 ,  H01L23/58

Abstract: A semiconductor device includes a metallization system positioned above a substrate and a die seal positioned at least in the metallization system and delimiting a die region. The die seal includes a via line feature having an axial length and including one or more first portions having a first target dimension and one or more second portions along the axial length. The one or more second portions have a second target dimension less than the first target dimension.

公开(公告)号：US10014234B2

公开(公告)日：2018-07-03

申请号：US15367888

申请日：2016-12-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Dirk Breuer ,  Maik Liebau ,  Matthias Lehr

IPC: H01L23/00 ,  H01L23/26 ,  H01L23/31 ,  H01L23/522 ,  H01L23/528 ,  H01L21/56 ,  H01L21/66 ,  H01L21/768

CPC classification number: H01L23/562 ,  H01L22/12 ,  H01L22/30 ,  H01L23/3107 ,  H01L23/585 ,  H01L2224/4903 ,  H01L2224/94 ,  H01L2924/0002 ,  H01L2924/00012

Abstract: The patterning technique used for forming sophisticated metallization systems of semiconductor devices may be monitored and evaluated more efficiently by incorporating at least one via line feature into the die seal. In this manner, high statistical significance may be obtained compared to conventional strategies, in which the respective test structures for evaluating patterning processes may be provided at specific sites in the frame region and/or die region. Moreover, by providing a “long” via line feature, superior sensitivity for variations of depth of focus may be achieved.

公开(公告)号：US20130234300A1

公开(公告)日：2013-09-12

申请号：US13870411

申请日：2013-04-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Axel Walter ,  Matthias Lehr

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/3677 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/552 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L2224/03 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05022 ,  H01L2224/05147 ,  H01L2224/05541 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/0558 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/06133 ,  H01L2224/1148 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/81191 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A bump structure or pillar structure formed above a metallization system of a complex semiconductor device may include a stress buffer layer, which may efficiently distribute the resulting mechanical stress which may typically occur during the chip package interaction due to a thermal mismatch of these components. The stress buffer layer comprises copper-based buffer regions that cover a significant portion of the overall surface, wherein a thickness of approximately 3-10 μm may also be used. Moreover, the buffer regions may efficiently replace aluminum as a terminal metal active region.

Abstract translation: 形成在复合半导体器件的金属化系统之上的凸起结构或柱结构可以包括应力缓冲层，其可以有效地分布由于这些部件的热失配而在芯片封装相互作用期间通常发生的所得到的机械应力。 应力缓冲层包括覆盖整个表面的重要部分的铜基缓冲区，其中也可以使用约3-10μm的厚度。 此外，缓冲区域可以有效地代替铝作为末端金属活性区域。