公开(公告)号：US09640514B1

公开(公告)日：2017-05-02

申请号：US15084004

申请日：2016-03-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Wei Lin ,  Troy L. Graves-Abe ,  Donald F. Canaperi ,  Spyridon Skordas ,  Matthew T. Shoudy ,  Binglin Miao ,  Raghuveer R. Patlolla ,  Sanjay C. Mehta

IPC: H01L25/065 ,  H01L21/762 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/76251 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L25/50 ,  H01L2224/29084 ,  H01L2224/29187 ,  H01L2224/32145 ,  H01L2224/83031 ,  H01L2224/83193 ,  H01L2224/832 ,  H01L2224/83896 ,  H01L2924/01005 ,  H01L2924/01007 ,  H01L2924/01008 ,  H01L2924/01014 ,  H01L2924/0503 ,  H01L2924/05442 ,  H01L2924/059 ,  H01L2924/20109 ,  H01L2924/206 ,  H01L2924/2064

Abstract: A bonding material stack for wafer-to-wafer bonding is provided. The bonding material stack may include a plurality of layers each including boron and nitrogen. In one embodiment, the plurality of layers may include: a first boron oxynitride layer for adhering to a wafer; a boron nitride layer over the first boron oxynitride layer; a second boron oxynitride layer over the boron nitride layer; and a silicon-containing boron oxynitride layer over the second boron oxynitride layer.

公开(公告)号：US09620481B2

公开(公告)日：2017-04-11

申请号：US14716300

申请日：2015-05-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Daniel C. Edelstein ,  Douglas C. La Tulipe, Jr. ,  Wei Lin ,  Deepika Priyadarshini ,  Spyridon Skordas ,  Tuan A. Vo ,  Kevin R. Winstel

IPC: H01L21/00 ,  H01L25/065 ,  H01L21/768 ,  H01L23/532 ,  H01L23/00 ,  H01L25/00 ,  H01L23/48

CPC classification number: H01L25/0657 ,  H01L21/76847 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76885 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/532 ,  H01L23/53233 ,  H01L23/5329 ,  H01L24/00 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/09 ,  H01L24/80 ,  H01L24/89 ,  H01L25/50 ,  H01L2224/03845 ,  H01L2224/05007 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05547 ,  H01L2224/05576 ,  H01L2224/05647 ,  H01L2224/05686 ,  H01L2224/08121 ,  H01L2224/08145 ,  H01L2224/08146 ,  H01L2224/80009 ,  H01L2224/80097 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01026 ,  H01L2924/01027 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01322 ,  H01L2924/05442 ,  H01L2924/00014 ,  H01L2924/20111 ,  H01L2924/00

Abstract: A metallic dopant element having a greater oxygen-affinity than copper is introduced into, and/or over, surface portions of copper-based metal pads and/or surfaces of a dielectric material layer embedding the copper-based metal pads in each of two substrates to be subsequently bonded. A dopant-metal silicate layer may be formed at the interface between the two substrates to contact portions of metal pads not in contact with a surface of another metal pad, thereby functioning as an oxygen barrier layer, and optionally as an adhesion material layer. A dopant metal rich portion may be formed in peripheral portions of the metal pads in contact with the dopant-metal silicate layer. A dopant-metal oxide portion may be formed in peripheral portions of the metal pads that are not in contact with a dopant-metal silicate layer.

公开(公告)号：US09466538B1

公开(公告)日：2016-10-11

申请号：US14951634

申请日：2015-11-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Spyridon Skordas ,  Subramanian S Iyer ,  Donald Francis Canaperi ,  Shidong Li ,  Wei Lin

IPC: H01L21/30 ,  H01L21/66 ,  H01L25/00 ,  H01L23/00 ,  H01L21/687 ,  H01L21/68 ,  H01L21/18 ,  H01L21/20

CPC classification number: H01L21/2007 ,  H01L21/187 ,  H01L21/67092 ,  H01L21/67248 ,  H01L21/67288 ,  H01L21/68 ,  H01L21/681 ,  H01L22/12 ,  H01L22/20 ,  H01L24/33 ,  H01L24/83 ,  H01L25/50 ,  H01L2224/27849 ,  H01L2224/83097 ,  H01L2224/83123 ,  H01L2224/83125 ,  H01L2224/83136 ,  H01L2224/83895

Abstract: A method of improving chip-to-chip alignment accuracy for circuitry-including wafer-to-wafer bonding. The method comprises providing separate stages for holding first and second circuitry-including wafers, each stage including a plurality of adjacent thermal actuators arranged in an array integrated with the stage; determining planar distortions of a bonding surface of the first and second circuitry-including wafers; mapping the planar distortions for each wafer based on the relative planar distortions thereon; deducing necessary local thermal expansion measurements for each wafer to compensate for the relative distortions based on the mapping; translating the thermal expansion measurements into a non-uniform wafer temperature profile model and a local heat flux profile model for each wafer; aligning the first and second wafers; and bonding the first and second wafers together. The bonding process includes simultaneously thermally treating at least one of the wafers in situ by individually adjusting the temperature of one or more thermal actuators in the array in accordance with the wafer temperature profile model and the local heat flux model to induce thermal expansion over a surface area corresponding to the dimensions of each adjusted thermal actuator.

Abstract translation: 一种提高芯片对芯片对准精度的方法，包括晶片与晶片的接合。 该方法包括提供用于保持包括第一和第二电路的晶片的分开的级，每个级包括多个相邻的热致动器，其布置成与该级一体化的阵列; 确定包含第一和第二电路的晶片的接合表面的平面失真; 基于其上的相对平面失真来映射每个晶片的平面失真; 推导每个晶片必要的局部热膨胀测量，以补偿基于映射的相对失真; 将热膨胀测量值转换为不均匀的晶片温度分布模型和每个晶片的局部热通量分布模型; 对准第一和第二晶片; 以及将所述第一和第二晶片结合在一起。 接合过程包括通过根据晶片温度分布模型和局部热通量模型单独调节阵列中的一个或多个热致动器的温度来同时热处理至少一个晶片，以在表面上引起热膨胀 面积对应于每个调节热致动器的尺寸。

公开(公告)号：US09401303B2

公开(公告)日：2016-07-26

申请号：US14449185

申请日：2014-08-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kangguo Cheng ,  Jonathan E. Faltermeier ,  Mukta G. Farooq ,  Wei Lin ,  Spyridon Skordas ,  Kevin R. Winstel

IPC: H01L21/762 ,  H01L27/12 ,  H01L21/02

CPC classification number: H01L21/76251 ,  H01L21/02304 ,  H01L21/02334 ,  H01L21/02345 ,  H01L21/31105 ,  H01L21/6835 ,  H01L21/76256 ,  H01L21/78 ,  H01L27/1203 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381

Abstract: The present invention relates generally to semiconductor structures and methods of manufacture and, more particularly, to the temporary bonding of a semiconductor wafer to handler wafer during processing. The semiconductor wafer may be temporarily bonded to the handler wafer by forming a sacrificial layer on a surface of a handler wafer, forming a first dielectric layer on a surface of the sacrificial layer, forming a second dielectric layer on a surface of a semiconductor wafer, and directly bonding the first dielectric layer and the second dielectric layer to form a bonding layer. After the semiconductor wafer is processed, it may be removed from the handler wafer along with the bonding layer by degrading the sacrificial layer with infrared radiation transmitted through the handler wafer.

Abstract translation: 本发明一般涉及半导体结构和制造方法，更具体地说，涉及在处理期间将半导体晶片临时粘接到处理器晶片。 半导体晶片可以通过在处理器晶片的表面上形成牺牲层而临时地结合到处理器晶片，在牺牲层的表面上形成第一电介质层，在半导体晶片的表面上形成第二电介质层， 并且直接接合第一介电层和第二介电层以形成接合层。 在处理半导体晶片之后，可以通过借助透射通过处理器晶片的红外辐射降低牺牲层，与粘合层一起从处理器晶片中去除。