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    Method to achieve ultra-high chip-to-chip alignment accuracy for wafer-to-wafer bonding process
    3.
    发明授权
    Method to achieve ultra-high chip-to-chip alignment accuracy for wafer-to-wafer bonding process 有权
    实现晶圆到晶片接合工艺的超高芯片对芯片对准精度的方法

    公开(公告)号：US09466538B1

    公开(公告)日：2016-10-11

    申请号：US14951634

    申请日：2015-11-25

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Spyridon Skordas ,  Subramanian S Iyer ,  Donald Francis Canaperi ,  Shidong Li ,  Wei Lin

    IPC: H01L21/30 ,  H01L21/66 ,  H01L25/00 ,  H01L23/00 ,  H01L21/687 ,  H01L21/68 ,  H01L21/18 ,  H01L21/20

    CPC classification number: H01L21/2007 ,  H01L21/187 ,  H01L21/67092 ,  H01L21/67248 ,  H01L21/67288 ,  H01L21/68 ,  H01L21/681 ,  H01L22/12 ,  H01L22/20 ,  H01L24/33 ,  H01L24/83 ,  H01L25/50 ,  H01L2224/27849 ,  H01L2224/83097 ,  H01L2224/83123 ,  H01L2224/83125 ,  H01L2224/83136 ,  H01L2224/83895

    Abstract: A method of improving chip-to-chip alignment accuracy for circuitry-including wafer-to-wafer bonding. The method comprises providing separate stages for holding first and second circuitry-including wafers, each stage including a plurality of adjacent thermal actuators arranged in an array integrated with the stage; determining planar distortions of a bonding surface of the first and second circuitry-including wafers; mapping the planar distortions for each wafer based on the relative planar distortions thereon; deducing necessary local thermal expansion measurements for each wafer to compensate for the relative distortions based on the mapping; translating the thermal expansion measurements into a non-uniform wafer temperature profile model and a local heat flux profile model for each wafer; aligning the first and second wafers; and bonding the first and second wafers together. The bonding process includes simultaneously thermally treating at least one of the wafers in situ by individually adjusting the temperature of one or more thermal actuators in the array in accordance with the wafer temperature profile model and the local heat flux model to induce thermal expansion over a surface area corresponding to the dimensions of each adjusted thermal actuator.

    Abstract translation: 一种提高芯片对芯片对准精度的方法，包括晶片与晶片的接合。 该方法包括提供用于保持包括第一和第二电路的晶片的分开的级，每个级包括多个相邻的热致动器，其布置成与该级一体化的阵列; 确定包含第一和第二电路的晶片的接合表面的平面失真; 基于其上的相对平面失真来映射每个晶片的平面失真; 推导每个晶片必要的局部热膨胀测量，以补偿基于映射的相对失真; 将热膨胀测量值转换为不均匀的晶片温度分布模型和每个晶片的局部热通量分布模型; 对准第一和第二晶片; 以及将所述第一和第二晶片结合在一起。 接合过程包括通过根据晶片温度分布模型和局部热通量模型单独调节阵列中的一个或多个热致动器的温度来同时热处理至少一个晶片，以在表面上引起热膨胀 面积对应于每个调节热致动器的尺寸。

    METHODS OF FORMING A PROTECTIVE LAYER ON AN INSULATING LAYER FOR PROTECTION DURING FORMATION OF CONDUCTIVE STRUCTURES
    4.
    发明申请
    METHODS OF FORMING A PROTECTIVE LAYER ON AN INSULATING LAYER FOR PROTECTION DURING FORMATION OF CONDUCTIVE STRUCTURES 审中-公开
    在形成导电结构时在绝缘层上形成保护层的保护方法

    公开(公告)号：US20160133572A1

    公开(公告)日：2016-05-12

    申请号：US14536083

    申请日：2014-11-07

    Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

    Inventor： Xunyuan Zhang ,  Wei Lin

    IPC: H01L23/532 ,  H01L21/02 ,  H01L21/768 ,  H01L21/033 ,  H01L23/528 ,  H01L21/3213

    CPC classification number: H01L21/0337 ,  H01L21/02244 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/76829 ,  H01L21/7684 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: One illustrative method disclosed herein includes, among other things, performing at least one etching process through an overall masking layer to define an opening in a layer of insulating material, wherein the overall masking layer is comprised of a patterned metal-silicate masking layer that is positioned on and in contact with the layer of insulating material and a patterned masking layer positioned on and in contact with the patterned metal-silicate masking layer, over-filling the opening with a conductive material and performing at least one planarization process so as to remove excess materials positioned outside of the opening above the patterned metal-silicate masking layer and thereby define a conductive structure that is positioned in the opening.

    Abstract translation: 本文中公开的一种说明性方法包括通过整体掩模层进行至少一个蚀刻工艺以限定绝缘材料层中的开口，其中整个掩模层由图案化的金属硅酸盐掩蔽层 定位在绝缘材料层上并与绝缘材料层接触并且与图案化的金属硅酸盐掩蔽层定位并与其接触的图案化掩模层，用导电材料过度填充该开口并执行至少一个平坦化处理以便去除 多余材料位于图案化的金属硅酸盐掩蔽层上方的开口的外侧，从而限定位于开口中的导电结构。

    Integrated circuit structure with refractory metal alignment marker and methods of forming same
    5.
    发明授权
    Integrated circuit structure with refractory metal alignment marker and methods of forming same 有权

    公开(公告)号：US09806032B1

    公开(公告)日：2017-10-31

    申请号：US15384741

    申请日：2016-12-20

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Wei Lin ,  Nailong He ,  Upinder Singh

    IPC: H01L23/544 ,  H01L49/02 ,  H01L23/522 ,  H01L27/06

    CPC classification number: H01L23/544 ,  H01L23/5223 ,  H01L23/5228 ,  H01L27/0682 ,  H01L28/75 ,  H01L2223/54426 ,  H01L2223/54453

    Abstract: The disclosure relates to integrated circuit (IC) structures and fabrication techniques. Methods according to the disclosure can include: providing a precursor structure including: a first inter-metal dielectric (IMD); a barrier dielectric positioned on the first IMD; forming an insulator on the barrier dielectric of the precursor structure, wherein an upper surface of the insulator includes a first trench and a second trench laterally separated from the first trench; forming an alignment marker over the precursor structure by filling the first trench with a first refractory metal film; forming a first metal-insulator-metal (MIM) electrode by filling the second trench with the first refractory metal film; recessing the insulator without exposing an upper surface of the barrier dielectric; forming a MIM dielectric layer on the insulator; and forming a second MIM electrode on the MIM dielectric layer, such that the second MIM electrode overlies a portion of the first MIM electrode.

    Handler wafer removal by use of sacrificial inert layer
    6.
    发明授权
    Handler wafer removal by use of sacrificial inert layer 有权
    通过使用牺牲惰性层来处理晶片去除

    公开(公告)号：US09401303B2

    公开(公告)日：2016-07-26

    申请号：US14449185

    申请日：2014-08-01

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Kangguo Cheng ,  Jonathan E. Faltermeier ,  Mukta G. Farooq ,  Wei Lin ,  Spyridon Skordas ,  Kevin R. Winstel

    IPC: H01L21/762 ,  H01L27/12 ,  H01L21/02

    CPC classification number: H01L21/76251 ,  H01L21/02304 ,  H01L21/02334 ,  H01L21/02345 ,  H01L21/31105 ,  H01L21/6835 ,  H01L21/76256 ,  H01L21/78 ,  H01L27/1203 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381

    Abstract: The present invention relates generally to semiconductor structures and methods of manufacture and, more particularly, to the temporary bonding of a semiconductor wafer to handler wafer during processing. The semiconductor wafer may be temporarily bonded to the handler wafer by forming a sacrificial layer on a surface of a handler wafer, forming a first dielectric layer on a surface of the sacrificial layer, forming a second dielectric layer on a surface of a semiconductor wafer, and directly bonding the first dielectric layer and the second dielectric layer to form a bonding layer. After the semiconductor wafer is processed, it may be removed from the handler wafer along with the bonding layer by degrading the sacrificial layer with infrared radiation transmitted through the handler wafer.

    Abstract translation: 本发明一般涉及半导体结构和制造方法，更具体地说，涉及在处理期间将半导体晶片临时粘接到处理器晶片。 半导体晶片可以通过在处理器晶片的表面上形成牺牲层而临时地结合到处理器晶片，在牺牲层的表面上形成第一电介质层，在半导体晶片的表面上形成第二电介质层， 并且直接接合第一介电层和第二介电层以形成接合层。 在处理半导体晶片之后，可以通过借助透射通过处理器晶片的红外辐射降低牺牲层，与粘合层一起从处理器晶片中去除。

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