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    Method of fabrication of a support structure for a semiconductor device
    5.
    发明申请
    Method of fabrication of a support structure for a semiconductor device 有权
    制造半导体器件的支撑结构的方法

    公开(公告)号：US20050014349A1

    公开(公告)日：2005-01-20

    申请号：US10735695

    申请日：2003-12-16

    申请人： Glen Carey ,  Ian Jenks ,  Alan Lewis ,  Rene Lujan ,  Hailong Zhou

    发明人： Glen Carey ,  Ian Jenks ,  Alan Lewis ,  Rene Lujan ,  Hailong Zhou

    IPC分类号： C30B1/00 ,  H01L21/00 ,  H01L21/20 ,  H01L21/36 ,  H01L33/00 ,  H01S5/02 ,  H01S5/183 ,  H01S5/323

    CPC分类号： H01S5/18305 ,  H01L21/02395 ,  H01L21/02543 ,  H01L21/02546 ,  H01L33/0079 ,  H01S5/0217 ,  H01S5/0224 ,  H01S5/141 ,  H01S5/323

    摘要： A method of fabricating a semiconductor device is described. In this method, a starting substrate of sufficient thickness is selected that has the required defect density levels, which may result in an undesirable doping level. Then a semiconductor layer having a desired doping level is formed on the starting substrate. The resulting semiconductor layer has the required defect density and doping levels for the final product application. After active components, electrical conductors, and any other needed structures are formed on the semiconductor layer, the starting substrate is removed leaving a desired thickness of the semiconductor layer. In a VECSEL application, the active components can be a gain cavity, where the semiconductor layer has the necessary defect density and doping levels to maximize wall plug efficiency (WPE). In one embodiment, the doping of the semiconductor layer is not uniform. For example, a majority of the layer is doped at a low level and the remainder is doped at a much higher level. This can result in improved WPE at particular thicknesses for the higher doped material.

    摘要翻译： 描述制造半导体器件的方法。 在该方法中，选择具有所需缺陷密度水平的足够厚度的起始衬底，这可能导致不期望的掺杂水平。 然后在起始衬底上形成具有期望的掺杂水平的半导体层。 所得到的半导体层具有所需的缺陷密度和最终产品应用的掺杂水平。 在有源部件之后，在半导体层上形成电导体和任何其它需要的结构，去除起始衬底，留出半导体层的所需厚度。 在VECSEL应用中，有源部件可以是增益腔，其中半导体层具有必要的缺陷密度和掺杂水平以最大化壁插拔效率（WPE）。 在一个实施例中，半导体层的掺杂不均匀。 例如，该层的大部分以低电平掺杂，其余部分以更高的水平掺杂。 这可以导致用于较高掺杂材料的特定厚度的改进的WPE。