公开(公告)号：US20070032971A1

公开(公告)日：2007-02-08

申请号：US11185131

申请日：2005-07-20

申请人： Goutam Dutta ,  Vineet Mishra

发明人： Goutam Dutta ,  Vineet Mishra

IPC分类号： G01R25/00 ,  G01R27/00

CPC分类号： G01R29/26 ,  G01R31/31709

摘要： A method and system is provided for determining noise components of an analog-to-digital converter. In one aspect of the invention, a method comprises providing an input signal to a signal input and a clock input of the ADC, outputting a plurality of samples at a sampled phase on the input signal for a plurality of sampled phases, and determining a jitter noise factor value, a reference noise factor value, and a total noise spectrum based on the plurality of samples for each of the plurality of sampled phases. A least means square algorithm is performed on the plurality of jitter noise factor values, reference noise factor values, and total noise spectra to estimate at least one of a jitter noise component and a reference noise component.

公开(公告)号：US07295937B2

公开(公告)日：2007-11-13

申请号：US11185131

申请日：2005-07-20

申请人： Goutam Dutta ,  Vineet Mishra

发明人： Goutam Dutta ,  Vineet Mishra

IPC分类号： G01R29/26

CPC分类号： G01R29/26 ,  G01R31/31709

摘要： A method and system is provided for determining noise components of an analog-to-digital converter. In one aspect of the invention, a method comprises providing an input signal to a signal input and a clock input of the ADC, outputting a plurality of samples at a sampled phase on the input signal for a plurality of sampled phases, and determining a jitter noise factor value, a reference noise factor value, and a total noise spectrum based on the plurality of samples for each of the plurality of sampled phases. A least means square algorithm is performed on the plurality of jitter noise factor values, reference noise factor values, and total noise spectra to estimate at least one of a jitter noise component and a reference noise component.

摘要翻译： 提供了一种用于确定模数转换器的噪声分量的方法和系统。 在本发明的一个方面，一种方法包括向ADC的信号输入端和时钟输入端提供输入信号，在多个采样相位的输入信号上以采样相位输出多个采样，并确定抖动 噪声因子值，参考噪声因子值和基于所述多个样本的多个样本的总噪声谱。 对多个抖动噪声因子值，参考噪声因子值和总噪声谱执行最小均方算法来估计抖动噪声分量和参考噪声分量中的至少一个。

公开(公告)号：US20130021182A1

公开(公告)日：2013-01-24

申请号：US13184570

申请日：2011-07-18

申请人： Vineet Mishra ,  Jayawardan Janardhanan ,  Samala Sreekiran ,  Meghna Agrawal

发明人： Vineet Mishra ,  Jayawardan Janardhanan ,  Samala Sreekiran ,  Meghna Agrawal

IPC分类号： H03M3/02

CPC分类号： H03M3/496 ,  H03M3/39 ,  H03M3/464

摘要： A continuous-time sigma-delta analog to digital converter (CTSD ADC) includes a comparator that samples the time integral of an analog signal at each rising edge and falling edge of a sampling clock. A feedback block, operating as a digital to analog converter, receives the outputs of the comparator and generates corresponding analog signals also at each rising and falling edge of the sampling clock. The feedback blocks are implemented as either switched-resistor or switched-current circuits. High signal-to-noise ratio (SNR) is achieved in the CTSD ADC without the need to use very high sampling clock frequencies. Compensation for excess loop delay is provided using a local feedback technique. In an embodiment, the sigma delta modulator in the CTSD ADC is implemented as a second order loop, and the comparator as a two-level comparator.

摘要翻译： 连续时间Σ-Δ模数转换器（CTSD ADC）包括在采样时钟的每个上升沿和下降沿采样模拟信号的时间积分的比较器。 作为数模转换器工作的反馈块接收比较器的输出，并在采样时钟的每个上升沿和下降沿也产生相应的模拟信号。 反馈块实现为开关电阻或开关电流电路。 在CTSD ADC中实现了高信噪比（SNR），而不需要使用非常高的采样时钟频率。 使用本地反馈技术提供多余回路延迟的补偿。 在一个实施例中，CTSD ADC中的Σ-Δ调制器被实现为二阶环路，比较器被实现为两电平比较器。

公开(公告)号：US08792650B2

公开(公告)日：2014-07-29

申请号：US13158236

申请日：2011-06-10

申请人： Vineet Mishra

发明人： Vineet Mishra

IPC分类号： A61F11/06 ,  H04B15/00

CPC分类号： H03F3/211 ,  H03F3/181 ,  H03F3/45475 ,  H03F3/45941 ,  H03F2203/45522 ,  H03F2203/45528 ,  H03F2203/45594

摘要： A driver circuit includes a first driver amplifier that is configured to generate a first output in response to a first reference voltage input and a first audio input; a second driver amplifier that is configured to generate a second output in response to the first reference voltage and a second audio input; and a common mode (CM) amplifier, coupled to the first driver amplifier and the second driver amplifier. The CM amplifier is configured to generate an output in response to a second reference voltage input, the first reference voltage input being a divided version of the output. Gains of the first driver amplifier, second driver amplifier and the CM amplifier are equal. Noise at the output appears across a plurality of resistors coupled at the outputs of the first driver amplifier, second driver amplifier and the CM amplifier and cancels with respect to the output of the CM amplifier.

摘要翻译： 驱动器电路包括：第一驱动器放大器，被配置为响应于第一参考电压输入和第一音频输入而产生第一输出; 第二驱动器放大器，被配置为响应于所述第一参考电压和第二音频输入而产生第二输出; 以及耦合到第一驱动器放大器和第二驱动器放大器的共模（CM）放大器。 CM放大器被配置为响应于第二参考电压输入而产生输出，第一参考电压输入是输出的分割版本。 第一个驱动器放大器，第二个驱动器放大器和CM放大器的增益相等。 输出端的噪声出现在耦合在第一驱动放大器，第二驱动器放大器和CM放大器的输出端的多个电阻器上，并相对于CM放大器的输出而被取消。

公开(公告)号：US20100253561A1

公开(公告)日：2010-10-07

申请号：US12416429

申请日：2009-04-01

申请人： Vineet Mishra ,  Samala Sreekiran

发明人： Vineet Mishra ,  Samala Sreekiran

IPC分类号： H03M1/66

CPC分类号： H03M1/0663 ,  H03M1/742

摘要： A low noise current steering digital-to-analog converter (DAC). The DAC includes a current reference for generating a bias current that biases a set of current elements. The set of current elements includes a reference element. The current reference includes a reference amplifier and a reference arm. The reference arm includes a reference resistor and the reference element. The DAC further includes a switch periodically coupling each current element including the reference element, to the reference resistor and an output of the DAC. This rotates the set of current elements and attenuates flicker noise from each of the set of current elements.

摘要翻译： 低噪音电流转向数模转换器（DAC）。 DAC包括用于产生偏置一组当前元件的偏置电流的电流参考。 当前元素的集合包括参考元素。 电流基准包括参考放大器和参考臂。 参考臂包括参考电阻和参考元件。 DAC还包括周期性地将包括参考元件的每个电流元件耦合到基准电阻器和DAC的输出的开关。 这使得电流元件组旋转并且衰减来自该组电流元件中的每一个的闪烁噪声。

公开(公告)号：US07042383B2

公开(公告)日：2006-05-09

申请号：US10904322

申请日：2004-11-04

申请人： Vineet Mishra ,  Visvesvaraya A. Pentakota

发明人： Vineet Mishra ,  Visvesvaraya A. Pentakota

IPC分类号： H03M1/14 ,  H03M1/42

CPC分类号： H03M1/168

摘要： An ADC implemented according to an aspect of the present invention contains a non-zero bit stage followed by a zero-bit stage. The non-zero bit stage generates a sub-code, which is used in generating a digital code corresponding to an input analog signal, and the zero-bit stage does not provide any such sub-codes. Such a feature may be attained by using a gain amplifier provided according to another aspect of the present invention. The gain amplifier contains a main-amplifier which operates as a zero bit stage, and is also used by the non-zero bit stage. The same capacitance value may be maintained between the input terminal and output terminal of the main-amplifier to implement the zero bit stage, which enables the main-amplifier to be implemented with a low gain.

摘要翻译： 根据本发明的一个方面实现的ADC包含非零位级，后面是零位级。 非零比特级产生用于产生对应于输入模拟信号的数字码的子码，零比特级不提供任何这样的子码。 这样的特征可以通过使用根据本发明的另一方面提供的增益放大器来实现。 增益放大器包含作为零位级工作的主放大器，也由非零位级使用。 可以在主放大器的输入端子和输出端子之间保持相同的电容值，以实现零位级，这使得能够以低增益实现主放大器。

公开(公告)号：US20050116760A1

公开(公告)日：2005-06-02

申请号：US10724517

申请日：2003-11-29

申请人： Anand Udupa ,  Visvesvaraya Pentakota ,  Shakti Rath ,  Gautam Nandi ,  Vineet Mishra ,  Ravishankar Ayyagari ,  Nitin Agarwal

发明人： Anand Udupa ,  Visvesvaraya Pentakota ,  Shakti Rath ,  Gautam Nandi ,  Vineet Mishra ,  Ravishankar Ayyagari ,  Nitin Agarwal

IPC分类号： H03F1/26 ,  H03F3/45 ,  H03F3/72 ,  H03L5/00

CPC分类号： H03F1/26 ,  H03F3/45188 ,  H03F3/45475 ,  H03F3/4565 ,  H03F3/45937 ,  H03F3/72

摘要： Low voltage transistors are used in high voltage environment. The low voltage transistors may be used in the path of processing of a signal to increase the throughput performance. By using high voltage supply associated with the high voltage environment, a higher SNR may be attained. Various techniques are implemented to ensure that the low voltage transistors are not damaged by prolonged exposure to high voltages.

摘要翻译： 低压晶体管用于高压环境。 低电压晶体管可用于处理信号的路径以增加吞吐量性能。 通过使用与高压环境相关联的高压电源，可以获得更高的信噪比。 实施各种技术以确保低电压晶体管不被长时间暴露于高电压而损坏。

公开(公告)号：US08604543B2

公开(公告)日：2013-12-10

申请号：US13537196

申请日：2012-06-29

申请人： Kamel Benaissa ,  Greg C. Baldwin ,  Vineet Mishra ,  Ananth Kamath

发明人： Kamel Benaissa ,  Greg C. Baldwin ,  Vineet Mishra ,  Ananth Kamath

IPC分类号： H01L21/70

CPC分类号： H01L21/82385 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/0922

摘要： An integrated circuit with a core PMOS transistor formed in a first n-well and an isolated DENMOS (iso-DENMOS) transistor formed in a second n-well where the depth and doping of the first and second n-wells are the same. A method of forming an integrated circuit with a core PMOS transistor formed in a first n-well and an iso-DENMOS transistor formed in a second n-well where the depth and doping of the first and second n-wells are the same.

摘要翻译： 形成在第一n阱中的核心PMOS晶体管和形成在第二n阱中的隔离DENMOS（iso-DENMOS）晶体管的集成电路，其中第一和第二n-阱的深度和掺杂相同。 形成集成电路的方法，其形成在第一n阱中形成的核心PMOS晶体管晶体管和形成在第二n阱中的等效DONMOS晶体管，其中第一和第二n-阱的深度和掺杂相同。

公开(公告)号：US07259609B2

公开(公告)日：2007-08-21

申请号：US10724989

申请日：2003-12-01

申请人： Visvesvaraya A. Pentakota ,  Vineet Mishra ,  Shakti Shankar Rath ,  Gautam Salil Nandi

发明人： Visvesvaraya A. Pentakota ,  Vineet Mishra ,  Shakti Shankar Rath ,  Gautam Salil Nandi

IPC分类号： H03K5/08 ,  H03L5/00

CPC分类号： H03F3/45937 ,  H03F3/45188 ,  H03F3/45475 ,  H03F3/4565 ,  H03F3/72

摘要： A clamping circuit containing a transistor and a current amplifier. The transistor is designed to turn on when the voltage at a node exceeds (falls below) a specified upper (lower) level. The current amplifier is designed to draw substantial amount of current when the transistor is turned on to clamp the voltage at the node to the desired level.

摘要翻译： 包含晶体管和电流放大器的钳位电路。 晶体管被设计成当节点的电压超过（低于）指定的上（下）电平时导通。 电流放大器被设计成在晶体管导通时吸取大量的电流，以将节点处的电压钳位到所需的电平。

公开(公告)号：US06977605B2

公开(公告)日：2005-12-20

申请号：US10887969

申请日：2004-07-09

申请人： Chun Chieh Lee ,  Visvesvaraya A. Pentakota ,  Vineet Mishra

发明人： Chun Chieh Lee ,  Visvesvaraya A. Pentakota ,  Vineet Mishra

IPC分类号： H03L7/081 ,  H03L7/089 ,  H03L7/10 ,  H03M1/06 ,  H03M1/08 ,  H03M1/16 ,  H03M1/44 ,  H03M1/38

CPC分类号： H03L7/0812 ,  H03L7/0805 ,  H03L7/0891 ,  H03L7/10 ,  H03L2207/14 ,  H03M1/0678 ,  H03M1/0818 ,  H03M1/167 ,  H03M1/442

摘要： A delay locked loop clock generation circuit (100) includes a delay locked loop circuit (18), a dummy delay line (40), and a watch dog circuit (32). The delay locked loop circuit includes a delay line (20), a phase detector (25), and a charge pump circuit (30) having an input connected to the output (27) of the phase detector and an output (23) producing a delay control signal (Vctrl) coupled to the stages of the delay line of the delay locked loop circuit. The stages of the delay line are precisely matched to those of the dummy delay line (40). Tap points of the dummy delay line are connected to inputs of the watchdog circuit (32), which operates to generate control signals (34A,B) applied to control the phase detector (25 and the charge pump circuit (30). Tap point signals of the delay line (20) are decoded to produce clock signals (52) for a pipeline ADC (54).

摘要翻译： 延迟锁定环形时钟产生电路（100）包括延迟锁定环电路（18），虚拟延迟线（40）和看门狗电路（32）。 延迟锁定环电路包括延迟线（20），相位检测器（25）和电荷泵电路（30），其具有连接到相位检测器的输出端（27）的输入端和产生 延迟控制信号（Vctr1）耦合到延迟锁定环路延迟线的级。 延迟线的级与虚拟延迟线（40）的级精确匹配。 虚拟延迟线的抽头点连接到看门狗电路（32）的输入端，其操作以产生用于控制相位检测器（25和电荷泵电路（30））的控制信号（34A，B）。 解码延迟线（20）的信号以产生流水线ADC（54）的时钟信号（52）。