公开(公告)号：US20060190846A1

公开(公告)日：2006-08-24

申请号：US11403332

申请日：2006-04-13

申请人： Habib Hichri ,  Xiao Liu ,  Vincent McGahay ,  Conal Murray ,  Jawahar Nayak ,  Thomas Shaw

发明人： Habib Hichri ,  Xiao Liu ,  Vincent McGahay ,  Conal Murray ,  Jawahar Nayak ,  Thomas Shaw

IPC分类号： G06F17/50

CPC分类号： H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： Stacked via pillars, such as metal via pillars, are provided at different and designated locations in IC chips to support the chip structure during processing and any related processing stresses such as thermal and mechanical stresses. These stacked via pillars connect and extend from a base substrate of the strip to a top oxide cap of the chip. The primary purpose of the stacked via pillars is to hold the chip structure together to accommodate any radial deformations and also to relieve any stress, thermal and/or mechanical, build-tip during processing or reliability testing. The stacked via pillars are generally not electrically connected to any active lines or vias, however in some embodiments the stacked via pillars can provide an additional function of providing an electrical connection in the chip.

摘要翻译： 通过支柱堆叠，例如金属通孔柱，在IC芯片的不同和指定位置处提供，以在加工过程中支持芯片结构以及任何相关的加工应力，例如热和机械应力。 这些堆叠的通孔柱从条带的基底衬底连接并延伸到芯片的顶部氧化物盖。 堆叠的通孔柱的主要目的是将芯片结构保持在一起以适应任何径向变形，并且还可以在处理或可靠性测试期间缓解任何应力，热和/或机械构造尖端。 堆叠的通孔柱通常不电连接到任何有源线或通孔，但是在一些实施例中，堆叠的通孔柱可以提供在芯片中提供电连接的附加功能。

公开(公告)号：US20050118803A1

公开(公告)日：2005-06-02

申请号：US10726140

申请日：2003-12-02

申请人： Habib Hichri ,  Xiao Liu ,  Vincent McGahay ,  Conal Murray ,  Jawahar Nayak ,  Thomas Shaw

发明人： Habib Hichri ,  Xiao Liu ,  Vincent McGahay ,  Conal Murray ,  Jawahar Nayak ,  Thomas Shaw

IPC分类号： H01L21/4763 ,  H01L23/00 ,  H01L23/58

CPC分类号： H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： Stacked via pillars, such as metal via pillars, are provided at different and designated locations in IC chips to support the chip structure during processing and any related processing stresses such as thermal and mechanical stresses. These stacked via pillars connect and extend from a base substrate of the strip to a top oxide cap of the chip. The primary purpose of the stacked via pillars is to hold the chip structure together to accommodate any radial deformations and also to relieve any stress, thermal and/or mechanical, build-up during processing or reliability testing. The stacked via pillars are generally not electrically connected to any active lines or vias, however in some embodiments the stacked via pillars can provide an additional function of providing an electrical connection in the chip.

摘要翻译： 通过支柱堆叠，例如金属通孔柱，在IC芯片的不同和指定位置处提供，以在加工期间支撑芯片结构以及任何相关的加工应力，例如热和机械应力。 这些堆叠的通孔柱从条带的基底衬底连接并延伸到芯片的顶部氧化物盖。 堆叠的通孔柱的主要目的是将芯片结构保持在一起以适应任何径向变形，并且还可以在处理或可靠性测试期间缓解任何应力，热和/或机械的积累。 堆叠的通孔柱通常不电连接到任何有源线或通孔，但是在一些实施例中，堆叠的通孔柱可以提供在芯片中提供电连接的附加功能。

公开(公告)号：US20060014376A1

公开(公告)日：2006-01-19

申请号：US11230841

申请日：2005-09-20

申请人： Birendra Agarwala ,  Conrad Barile ,  Hormazdyar Dalal ,  Brett Engel ,  Michael Lane ,  Ernest Levine ,  Xiao Liu ,  Vincent McGahay ,  John McGrath ,  Conal Murray ,  Jawahar Nayak ,  Du Nguyen ,  Hazara Rathore ,  Thomas Shaw

发明人： Birendra Agarwala ,  Conrad Barile ,  Hormazdyar Dalal ,  Brett Engel ,  Michael Lane ,  Ernest Levine ,  Xiao Liu ,  Vincent McGahay ,  John McGrath ,  Conal Murray ,  Jawahar Nayak ,  Du Nguyen ,  Hazara Rathore ,  Thomas Shaw

IPC分类号： H01L21/4763 ,  H01L21/44 ,  H01L21/31

CPC分类号： H01L23/53295 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76838 ,  H01L23/5226 ,  H01L2924/0002 ,  Y10T428/24917 ,  H01L2924/00

摘要： A multilevel semiconductor integrated circuit (IC) structure including a first interconnect level including a layer of dielectric material over a semiconductor substrate, the layer of dielectric material comprising a dense material for passivating semiconductor devices and local interconnects underneath; multiple interconnect layers of dielectric material formed above the layer of dense dielectric material, each layer of dielectric material including at least a layer of low-k dielectric material; and, a set of stacked via-studs in the low-k dielectric material layers, each of said set of stacked via studs interconnecting one or more patterned conductive structures, a conductive structure including a cantilever formed in the low-k dielectric material. The dielectric layer of each of the multiple interconnection levels includes a soft low-k dielectric material, wherein the cantilever and set of stacked via-studs are integrated within the soft low-k dielectric material to increase resistance to thermal fatigue crack formation. In one embodiment, each of the set of stacked via-studs in the low-k dielectric material layers is provided with a cantilever, such that the cantilevers are interwoven by connecting a cantilever on one level to a bulk portion of the conductor line on adjacent levels of interconnection, thereby increasing flexibility of stacked via-studs between interconnection levels.

摘要翻译： 一种多级半导体集成电路（IC）结构，包括在半导体衬底上包括电介质材料层的第一互连电平，所述介电材料层包括用于钝化半导体器件的致密材料和其下的局部互连; 形成在致密电介质材料层之上的电介质材料的多个互连层，每层介电材料包括至少一层低k电介质材料; 以及在低k电介质材料层中的一组堆叠的通孔螺钉，每组所述一组堆叠通孔柱互连一个或多个图案化导电结构，包括形成在低k电介质材料中的悬臂的导电结构。 多个互连级别中的每一个的电介质层包括软的低k电介质材料，其中悬臂和一组堆叠的通孔螺钉集成在软低k电介质材料内，以增加对热疲劳裂纹形成的抵抗力。 在一个实施例中，低k电介质材料层中的每组叠置通孔螺柱设置有悬臂，使得悬臂通过将一个级上的悬臂连接到相邻的导体线的主体部分而交织 互连级别，从而增加互连级别之间堆叠通孔的灵活性。

公开(公告)号：US20050086628A1

公开(公告)日：2005-04-21

申请号：US10687475

申请日：2003-10-16

申请人： Ronald Filippi ,  Giovanni Fiorenza ,  Xiao Liu ,  Conal Murray ,  Gregory Northrop ,  Thomas Shaw ,  Richard Wachnik ,  Mary Yvonne Wisniewski

发明人： Ronald Filippi ,  Giovanni Fiorenza ,  Xiao Liu ,  Conal Murray ,  Gregory Northrop ,  Thomas Shaw ,  Richard Wachnik ,  Mary Yvonne Wisniewski

IPC分类号： G06F17/50 ,  G06F19/00

CPC分类号： G06F17/5018

摘要： A method for analyzing circuit designs includes discretizing a design representation into pixel elements representative of a structure in the design and determining at least one property for each pixel element representing a portion of the design. Then, a response of the design is determined due to local properties across the design.

摘要翻译： 用于分析电路设计的方法包括将设计表示离散成代表设计中的结构的像素元素，并且为表示设计的一部分的每个像素元素确定至少一个属性。 然后，由于设计中的局部属性，确定了设计的响应。

公开(公告)号：US20080118717A1

公开(公告)日：2008-05-22

申请号：US12018640

申请日：2008-01-23

申请人： Son Nguyen ,  Michael Lane ,  Stephen Gates ,  Xiao Liu ,  Vincent McGahay ,  Sanjay Mehta ,  Thomas Shaw

发明人： Son Nguyen ,  Michael Lane ,  Stephen Gates ,  Xiao Liu ,  Vincent McGahay ,  Sanjay Mehta ,  Thomas Shaw

IPC分类号： B32B3/00

CPC分类号： H01L21/3148 ,  H01L21/02126 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/3122 ,  H01L21/76807 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76832 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10T428/24802 ,  H01L2924/00

摘要： The present invention provides a hardmask that is located on a surface of a low k dielectric material having at least one conductive feature embedded therein. The hardmask includes a lower region of a hermetic oxide material located adjacent to the low k dielectric material and an upper region comprising atoms of Si, C and H located above the hermetic oxide material. The present invention also provides a method of fabricating the inventive hardmask as well as a method to form an interconnect structure containing the same.

公开(公告)号：US20060091559A1

公开(公告)日：2006-05-04

申请号：US10981233

申请日：2004-11-04

申请人： Son Nguyen ,  Michael Lane ,  Stephen Gates ,  Xiao Liu ,  Vincent McGahay ,  Sanjay Mehta ,  Thomas Shaw

发明人： Son Nguyen ,  Michael Lane ,  Stephen Gates ,  Xiao Liu ,  Vincent McGahay ,  Sanjay Mehta ,  Thomas Shaw

IPC分类号： H01L21/4763 ,  H01L23/52 ,  H01L21/31

CPC分类号： H01L21/3148 ,  H01L21/02126 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/3122 ,  H01L21/76807 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76832 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10T428/24802 ,  H01L2924/00

摘要： The present invention provides a hardmask that is located on a surface of a low k dielectric material having at least one conductive feature embedded therein. The hardmask includes a lower region of a hermetic oxide material located adjacent to the low k dielectric material and an upper region comprising atoms of Si, C and H located above the hermetic oxide material. The present invention also provides a method of fabricating the inventive hardmask as well as a method to form an interconnect structure containing the same.

公开(公告)号：US20060258159A1

公开(公告)日：2006-11-16

申请号：US11130078

申请日：2005-05-16

申请人： Matthew Colburn ,  Ricardo Donaton ,  Conal Murray ,  Satyanarayana Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Theodorus Eduardus Fransiscus Standaert ,  Xiao Liu

发明人： Matthew Colburn ,  Ricardo Donaton ,  Conal Murray ,  Satyanarayana Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Theodorus Eduardus Fransiscus Standaert ,  Xiao Liu

IPC分类号： H01B13/00 ,  H01L21/302 ,  B44C1/22

CPC分类号： H01L21/32139 ,  H01L21/0271 ,  H01L21/31144 ,  H01L21/7682

摘要： A process for preparing an electronics structure involves coating a substrate stack with a sacrificial multilayer hardmask stack, developing a pattern in a resist layer coated on a topmost layer of the multilayer hardmask stack, transferring the pattern into the hardmask stack, blocking a portion of the pattern, and then transferring an unblocked portion of the pattern into the substrate stack. Electronics structures prepared with the process are useful to prepare electronics devices, such as computers and the like. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader quickly to ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the appended issued claims.

摘要翻译： 用于制备电子结构的方法包括用牺牲多层硬掩模堆叠涂覆衬底叠层，在涂覆在多层硬掩模堆叠的最上层上的抗蚀剂层中形成图案，将图案转移到硬掩模堆叠中，阻挡部分 图案，然后将图案的未封闭部分转印到基底叠层中。 使用该方法制备的电子结构对制备电子设备（例如计算机等）是有用的。 要强调的是，该摘要被提供以符合要求抽象的规则，这将允许搜索者或其他读者快速地确定技术公开的主题。 提交它的理解是，它不会用于解释或限制所附权利要求的范围或含义。

公开(公告)号：US20080044668A1

公开(公告)日：2008-02-21

申请号：US11034479

申请日：2005-01-13

申请人： Christos Dimitrakopoulos ,  Stephen Gates ,  Alfred Grill ,  Michael Lane ,  Eric Liniger ,  Xiao Liu ,  Son Nguyen ,  Deborah Neumayer ,  Thomas Shaw

发明人： Christos Dimitrakopoulos ,  Stephen Gates ,  Alfred Grill ,  Michael Lane ,  Eric Liniger ,  Xiao Liu ,  Son Nguyen ,  Deborah Neumayer ,  Thomas Shaw

IPC分类号： B32B9/04 ,  B32B13/04

CPC分类号： H01L21/76834 ,  C23C16/30 ,  C23C16/56 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/02348 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/31633 ,  H01L21/76801 ,  H01L21/76825 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  Y10T428/249953 ,  Y10T428/249969 ,  Y10T428/249979

摘要： A method for forming a ultralow dielectric constant layer with controlled biaxial stress is described incorporating the steps of forming a layer containing Si, C, O and H by one of PECVD and spin-on coating and curing the film in an environment containing very low concentrations of oxygen and water each less than 10 ppm. A material is also described by using the method with a dielectric constant of not more than 2.8. The invention overcomes the problem of forming films with low biaxial stress less than 46 MPa.

摘要翻译： 描述了形成具有受控双轴应力的超低介电常数层的方法，其包括以下步骤：通过PECVD和旋涂方法之一形成包含Si，C，O和H的层，并在含有非常低的浓度的环境中固化该膜 的氧和水各自小于10ppm。 还通过使用介电常数不大于2.8的方法描述材料。 本发明克服了低双轴应力低于46MPa的薄膜形成问题。

公开(公告)号：US08222454B2

公开(公告)日：2012-07-17

申请号：US12517379

申请日：2007-11-28

申请人： Lin Ai ,  Xiao Liu

发明人： Lin Ai ,  Xiao Liu

IPC分类号： C07C233/58

CPC分类号： C07C231/20 ,  C07B2200/07 ,  C07C2601/02 ,  C07C237/24

摘要： The present invention discloses a process for preparing optically pure milnacipran and their pharmaceutically acceptable salts, which adopts racemic milnacipran as starting material, tartaric acid derivatives and their compositions as resolving agents to resolve.

摘要翻译： 本发明公开了一种制备光学纯米那普仑及其药学上可接受的盐的方法，其采用外消旋米那普兰作为起始原料，酒石酸衍生物及其组合物作为分离剂进行分解。

公开(公告)号：US20100314307A1

公开(公告)日：2010-12-16

申请号：US12518009

申请日：2007-03-08

申请人： Xiao Liu ,  Taili Zhou

发明人： Xiao Liu ,  Taili Zhou

IPC分类号： B01J20/22 ,  A61L2/16 ,  B65F1/14

CPC分类号： A61M1/0001 ,  A61M1/0017 ,  A61M1/0096 ,  B65F1/0006 ,  B65F2210/102

摘要： This invention relates to a medical sewage treater, which consists of an article storing bag and water absorbing material, wherein the water absorbing material is a super absorbent polymer and is adhered to the inner wall of the article storing bag or set in the article storing bag. After medical sewage has flowed into the article storing bag, the water absorbing material absorbs water and expands so as to make the treated medical sewage become a colloid or solid of poor flowability such that it is convenient and safe in transportation and can effectively overcome the disadvantages in the prior art, such as uneasily stacking, leakage and thereby pollution during the transportation of the medical sewage. The invention is also applicable to collection and treatment of other deleterious sewage in daily life.

摘要翻译： 本发明涉及一种医疗污水处理器，其由物品收纳袋和吸水材料组成，其中吸水材料为超吸收性聚合物，并且粘附到物品收纳袋的内壁或设置在物品收纳袋中 。 医疗污水流入物品收纳袋后，吸水材料吸水并膨胀，使处理后的医用污水成为流动性差的胶体或固体，运输方便安全，可有效克服缺点 在现有技术中，例如在运输医疗污水期间不安地堆放，泄漏以及污染。 本发明也适用于日常生活中其他有害污水的收集处理。