公开(公告)号：US20080118717A1

公开(公告)日：2008-05-22

申请号：US12018640

申请日：2008-01-23

申请人： Son Nguyen ,  Michael Lane ,  Stephen Gates ,  Xiao Liu ,  Vincent McGahay ,  Sanjay Mehta ,  Thomas Shaw

发明人： Son Nguyen ,  Michael Lane ,  Stephen Gates ,  Xiao Liu ,  Vincent McGahay ,  Sanjay Mehta ,  Thomas Shaw

IPC分类号： B32B3/00

CPC分类号： H01L21/3148 ,  H01L21/02126 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/3122 ,  H01L21/76807 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76832 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10T428/24802 ,  H01L2924/00

摘要： The present invention provides a hardmask that is located on a surface of a low k dielectric material having at least one conductive feature embedded therein. The hardmask includes a lower region of a hermetic oxide material located adjacent to the low k dielectric material and an upper region comprising atoms of Si, C and H located above the hermetic oxide material. The present invention also provides a method of fabricating the inventive hardmask as well as a method to form an interconnect structure containing the same.

公开(公告)号：US20060091559A1

公开(公告)日：2006-05-04

申请号：US10981233

申请日：2004-11-04

申请人： Son Nguyen ,  Michael Lane ,  Stephen Gates ,  Xiao Liu ,  Vincent McGahay ,  Sanjay Mehta ,  Thomas Shaw

发明人： Son Nguyen ,  Michael Lane ,  Stephen Gates ,  Xiao Liu ,  Vincent McGahay ,  Sanjay Mehta ,  Thomas Shaw

IPC分类号： H01L21/4763 ,  H01L23/52 ,  H01L21/31

CPC分类号： H01L21/3148 ,  H01L21/02126 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/3122 ,  H01L21/76807 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76832 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10T428/24802 ,  H01L2924/00

摘要： The present invention provides a hardmask that is located on a surface of a low k dielectric material having at least one conductive feature embedded therein. The hardmask includes a lower region of a hermetic oxide material located adjacent to the low k dielectric material and an upper region comprising atoms of Si, C and H located above the hermetic oxide material. The present invention also provides a method of fabricating the inventive hardmask as well as a method to form an interconnect structure containing the same.

公开(公告)号：US20060189133A1

公开(公告)日：2006-08-24

申请号：US11063152

申请日：2005-02-22

申请人： Christos Dimitrakopoulos ,  Stephen Gates ,  Vincent McGahay ,  Sanjay Mehta

发明人： Christos Dimitrakopoulos ,  Stephen Gates ,  Vincent McGahay ,  Sanjay Mehta

IPC分类号： H01L21/4763 ,  H01L21/44 ,  H01L23/48

CPC分类号： H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76885 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to methods of improving the fabrication of interconnect structures of the single or dual damascene type, in which there is no problem of hard mask retention or of conductivity between the metal lines after fabrication. The methods of the present invention include at least steps of chemical mechanical polishing and UV exposure or chemical repair treatment which steps improve the reliability of the interconnect structure formed. The present invention also relates to an interconnect structure which include a porous ultra low k dielectric of the SiCOH type in which the surface layer thereof has been modified so as to form a gradient layer that has both a density gradient and a C content gradient.

摘要翻译： 本发明涉及改进单镶嵌型或双镶嵌型互连结构的制造方法，其中在制造之后金属线之间没有硬掩模保持或导电性问题。 本发明的方法包括化学机械抛光和紫外线曝光或化学修复处理的至少步骤，这些步骤提高了形成的互连结构的可靠性。 本发明还涉及一种互连结构，其包括SiCOH型的多孔超低k电介质，其中其表面层被修饰以形成具有密度梯度和C含量梯度的梯度层。

公开(公告)号：US20070228570A1

公开(公告)日：2007-10-04

申请号：US11763135

申请日：2007-06-14

申请人： Christos Dimitrakopoulos ,  Stephen Gates ,  Vincent McGahay ,  Sanjay Mehta

发明人： Christos Dimitrakopoulos ,  Stephen Gates ,  Vincent McGahay ,  Sanjay Mehta

IPC分类号： H01L23/532

CPC分类号： H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76885 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to methods of improving the fabrication of interconnect structures of the single or dual damascene type, in which there is no problem of hard mask retention or of conductivity between the metal lines after fabrication. The methods of the present invention include at least steps of chemical mechanical polishing and UV exposure or chemical repair treatment which steps improve the reliability of the interconnect structure formed. The present invention also relates to an interconnect structure which include a porous ultra low k dielectric of the SiCOH type in which the surface layer thereof has been modified so as to form a gradient layer that has both a density gradient and a C content gradient.

摘要翻译： 本发明涉及改进单镶嵌型或双镶嵌型互连结构的制造方法，其中在制造之后金属线之间没有硬掩模保持或导电性问题。 本发明的方法包括化学机械抛光和紫外线曝光或化学修复处理的至少步骤，这些步骤提高了形成的互连结构的可靠性。 本发明还涉及一种互连结构，其包括SiCOH型的多孔超低k电介质，其中其表面层被修饰以形成具有密度梯度和C含量梯度的梯度层。

公开(公告)号：US20070072412A1

公开(公告)日：2007-03-29

申请号：US11162883

申请日：2005-09-27

申请人： Derren Dunn ,  Nicholas Fuller ,  Catherine Labelle ,  Vincent McGahay ,  Sanjay Mehta ,  Henry Nye III

发明人： Derren Dunn ,  Nicholas Fuller ,  Catherine Labelle ,  Vincent McGahay ,  Sanjay Mehta ,  Henry Nye III

IPC分类号： H01L21/4763 ,  H01L21/311

CPC分类号： H01L21/31138 ,  H01L21/02118 ,  H01L21/02123 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/31116 ,  H01L21/31608 ,  H01L21/76831

摘要： Prevention of damage to an interlevel dielectric (ILD) is provided by forming an opening (e.g., trench) in the ILD, and sputtering a dielectric film onto a sidewall of the opening by overetching into a layer of the dielectric below or within the ILD during forming of the opening. The re-sputtered film protects the sidewall of the opening from subsequent plasma/ash processes and seals the porous dielectric surface along the sidewall and bottom without impacting overall process throughput. A semiconductor structure resulting from the above process is also disclosed.

摘要翻译： 通过在ILD中形成开口（例如，沟槽）来提供对层间电介质（ILD）的损坏的防止，并且通过在ILD内或在ILD内过度蚀刻到电介质层中，将电介质膜溅射到开口的侧壁上 形成开口。 再溅射的膜保护开口的侧壁不受后续的等离子体/灰分过程的影响，并且沿着侧壁和底部密封多孔电介质表面，而不影响整个工艺流程。 还公开了由上述方法得到的半导体结构。

公开(公告)号：US08790991B2

公开(公告)日：2014-07-29

申请号：US13011546

申请日：2011-01-21

申请人： Jason E. Cummings ,  Balasubramanian S. Haran ,  Hemanth Jagannathan ,  Sanjay Mehta

发明人： Jason E. Cummings ,  Balasubramanian S. Haran ,  Hemanth Jagannathan ,  Sanjay Mehta

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/06

CPC分类号： H01L21/76224 ,  H01L21/02107 ,  H01L21/823481 ,  H01L21/823878 ,  H01L29/0649 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/7833

摘要： A shallow trench isolation region is provided in which void formation is substantially or totally eliminated therefrom. The shallow trench isolation mitigates active shorts between two active regions of a semiconductor substrate. The shallow trench isolation region includes a bilayer liner which is present on sidewalls and a bottom wall of a trench that is formed in a semiconductor substrate. The bilayer liner of the present disclosure includes, from bottom to top, a shallow trench isolation liner, e.g., a semiconductor oxide and/or nitride, and a high k liner, e.g., a dielectric material having a dielectric constant that is greater than silicon oxide.

摘要翻译： 提供浅沟槽隔离区域，其中空隙形成基本上或完全从其中消除。 浅沟槽隔离减轻半导体衬底的两个有源区域之间的有源短路。 浅沟槽隔离区域包括存在于形成在半导体衬底中的沟槽的侧壁和底壁上的双层衬垫。 本公开的双层衬垫包括从底部到顶部的浅沟槽隔离衬垫，例如半导体氧化物和/或氮化物，以及高k衬里，例如介电常数大于硅的介电材料 氧化物。

公开(公告)号：US20130264641A1

公开(公告)日：2013-10-10

申请号：US13442168

申请日：2012-04-09

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Sanjay Mehta ,  Stefan Schmitz

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Sanjay Mehta ,  Stefan Schmitz

IPC分类号： H01L27/088 ,  H01L21/762 ,  H01L21/336

CPC分类号： H01L21/84 ,  H01L21/76283 ,  H01L27/1203

摘要： A thin BOX ETSOI device with robust isolation and method of manufacturing. The method includes providing a wafer with at least a pad layer overlying a first semiconductor layer overlying an oxide layer overlying a second semiconductor layer, wherein the first semiconductor layer has a thickness of 10 nm or less. The process continues with etching a shallow trench into the wafer, extending partially into the second semiconductor layer and forming first spacers on the sidewalls of said shallow trench. After spacer formation, the process continues by etching an area directly below and between the first spacers, exposing the underside of the first spacers, forming second spacers covering all exposed portions of the first spacers, wherein the pad oxide layer is removed, and forming a gate structure over the first semiconductor wafer.

摘要翻译： 薄型BOX ETSOI器件，具有强大的隔离性和制造方法。 该方法包括提供晶片至少一覆盖在覆盖第二半导体层的氧化物层上的第一半导体层的焊盘层，其中第一半导体层具有10nm或更小的厚度。 该过程继续蚀刻到晶片中的浅沟槽，部分地延伸到第二半导体层中并且在所述浅沟槽的侧壁上形成第一间隔物。 在间隔物形成之后，该过程继续蚀刻直接在第一间隔物下面和之间的区域，暴露第一间隔物的下侧，形成覆盖第一间隔物的所有暴露部分的第二间隔区，其中除去氧化垫层， 第一半导体晶片上的栅极结构。

公开(公告)号：US08476743B2

公开(公告)日：2013-07-02

申请号：US13228857

申请日：2011-09-09

申请人： Son Van Nguyen ,  Alfred Grill ,  Thomas J. Haigh, Jr. ,  Sanjay Mehta

发明人： Son Van Nguyen ,  Alfred Grill ,  Thomas J. Haigh, Jr. ,  Sanjay Mehta

IPC分类号： H01L23/58 ,  H01L21/31 ,  C23C8/54 ,  B05D5/12

CPC分类号： H01L21/02112 ,  H01B3/12 ,  H01L21/02274 ,  H01L21/02318 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/53252 ,  H01L23/53276 ,  H01L29/1054 ,  H01L29/1606 ,  H01L29/456 ,  H01L29/4908 ,  H01L29/4983 ,  H01L29/78648 ,  H01L2924/0002 ,  H01L2924/00

摘要： A carbon-rich carbon boron nitride dielectric film having a dielectric constant of equal to, or less than 3.6 is provided that can be used as a component in various electronic devices. The carbon-rich carbon boron nitride dielectric film has a formula of CxByNz wherein x is 35 atomic percent or greater, y is from 6 atomic percent to 32 atomic percent and z is from 8 atomic percent to 33 atomic percent.

摘要翻译： 提供具有等于或小于3.6的介电常数的富碳碳氮化硼介电膜，其可用作各种电子器件中的组分。 富碳碳氮化硼电介质膜具有C x B y N z的化学式，其中x为35原子％以上，y为6原子％〜32原子％，z为8原子％〜33原子％。

公开(公告)号：US20130032945A1

公开(公告)日：2013-02-07

申请号：US13197325

申请日：2011-08-03

申请人： Qinghuang Lin ,  Sanjay Mehta ,  Hosadurga Shobha

发明人： Qinghuang Lin ,  Sanjay Mehta ,  Hosadurga Shobha

IPC分类号： H01L23/522 ,  H01L21/768

CPC分类号： H01L23/5222 ,  H01L21/768 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L23/53295 ,  H01L2221/1026 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure and methods for making the same include sidewall portions of an interlevel dielectric layer. The sidewall portions have a width less than a minimum feature size for a given lithographic technology and the width is formed by a thickness of the interlevel dielectric layer when conformally formed on vertical surfaces of a mandrel. The sidewall portions form spaced-apart openings. Conductive structures fill the spaced-apart openings and are separated by the sidewall portions to form single damascene structures.

公开(公告)号：US20130015512A1

公开(公告)日：2013-01-17

申请号：US13605260

申请日：2012-09-06

申请人： Balasubramanian S. Haran ,  Hemanth Jagannathan ,  Sivananda K. Kanakasabapathy ,  Sanjay Mehta

发明人： Balasubramanian S. Haran ,  Hemanth Jagannathan ,  Sivananda K. Kanakasabapathy ,  Sanjay Mehta

IPC分类号： H01L29/78

CPC分类号： H01L29/66772 ,  H01L29/6653 ,  H01L29/78621

摘要： A gate dielectric is patterned after formation of a first gate spacer by anisotropic etch of a conformal dielectric layer to minimize overetching into a semiconductor layer. In one embodiment, selective epitaxy is performed to sequentially form raised epitaxial semiconductor portions, a disposable gate spacer, and raised source and drain regions. The disposable gate spacer is removed and ion implantation is performed into exposed portions of the raised epitaxial semiconductor portions to form source and drain extension regions. In another embodiment, ion implantation for source and drain extension formation is performed through the conformal dielectric layer prior to an anisotropic etch that forms the first gate spacer. The presence of the raised epitaxial semiconductor portions or the conformation dielectric layer prevents complete amorphization of the semiconductor material in the source and drain extension regions, thereby enabling regrowth of crystalline source and drain extension regions.