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    Method for manufacturing a semiconductor device
    3.
    发明授权
    Method for manufacturing a semiconductor device 失效
    半导体器件的制造方法

    公开(公告)号：US07118975B2

    公开(公告)日：2006-10-10

    申请号：US10872360

    申请日：2004-06-22

    申请人： Jae-Jong Han ,  Young-Wook Park ,  Jae-Hyun Yeo

    发明人： Jae-Jong Han ,  Young-Wook Park ,  Jae-Hyun Yeo

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66621 ,  H01L21/28123 ,  H01L21/76235 ,  H01L21/823481 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10876

    摘要： Provided is a method for manufacturing semiconductor devices including channel trenches that are separated by isolation structures. According to the process, the substrate is etched to form isolation trenches after which a sidewall oxide layer, a liner nitride layer and a field oxide layer are subsequently formed on the substrate and in the isolation trenches. The substrate is then planarized to remove upper portions of the sidewall oxide layer, the liner nitride layer and the field oxide layer to expose surface portions of the substrate between adjacent isolation trench structures. Channel trenches are then formed in the exposed surface portions of the substrate leaving residual substrate regions adjacent the isolation trench structures. These residual substrate regions are then oxidized and removed to form improved second channel trenches for the formation of transistor regions.

    摘要翻译： 提供一种半导体器件的制造方法，其包括由隔离结构分离的沟槽。 根据该过程，蚀刻衬底以形成隔离沟槽，之后随后在衬底和隔离沟槽中形成侧壁氧化物层，衬里氮化物层和场氧化物层。 然后将衬底平坦化以除去侧壁氧化物层，衬里氮化物层和场氧化物层的上部，以暴露在相邻的隔离沟槽结构之间的衬底的表面部分。 然后在衬底的暴露的表面部分中形成通道沟槽，留下邻近隔离沟槽结构的残余衬底区域。 然后将这些残留的衬底区域氧化并除去以形成用于形成晶体管区域的改进的第二沟道沟槽。

    Plasma enhanced chemical vapor deposition apparatus and method for forming nitride layer using the same
    5.
    发明授权
    Plasma enhanced chemical vapor deposition apparatus and method for forming nitride layer using the same 失效
    等离子体增强化学气相沉积装置和使用其形成氮化物层的方法

    公开(公告)号：US06828254B2

    公开(公告)日：2004-12-07

    申请号：US10277801

    申请日：2002-10-23

    申请人： Jae-Jong Han ,  Kyoung-Seok Kim ,  Byung-Ho Ahn ,  Seung Mok Shin ,  Hwa-Sik Kim ,  Hong-Bae Park

    发明人： Jae-Jong Han ,  Kyoung-Seok Kim ,  Byung-Ho Ahn ,  Seung Mok Shin ,  Hwa-Sik Kim ,  Hong-Bae Park

    IPC分类号： H01L2131

    CPC分类号： C23C16/4558 ,  C23C16/345 ,  C23C16/4404 ,  C23C16/4405 ,  C23C16/505 ,  H01J37/3244 ,  H01J37/32623

    摘要： A plasma enhanced chemical vapor deposition apparatus and a method of forming a nitride layer using the same, wherein the plasma enhanced CVD apparatus includes a process chamber including an upper chamber with a dome shape, a lower chamber, and an insulator therebetween, a gas distributing ring, a susceptor for supporting a wafer and heating the process chamber, a plasma compensation ring surrounding the susceptor, a vacuum pump and an electric power source connected to the process chamber. The gas distributing ring has a plurality of upwardly inclined nozzles, allowing upward distribution of reactive gases. The method of forming a nitride layer includes forming a protective film on inner walls of a process chamber, the protective film having at least two layers of differeing dielectric constant, and sequentially supplying reactive gases to the process chamber. A nitride layer formed thereby has low hydrogen content, good density and oxidation resistance.

    摘要翻译： 一种等离子体增强化学气相沉积装置和使用其形成氮化物层的方法，其中等离子体增强CVD装置包括处理室，该处理室包括具有圆顶形状的上室，下室和位于其间的绝缘体，气体分布 环，用于支撑晶片并加热处理室的基座，围绕基座的等离子体补偿环，真空泵和连接到处理室的电源。 气体分配环具有多个向上倾斜的喷嘴，允许反应气体向上分配。 形成氮化物层的方法包括在处理室的内壁上形成保护膜，所述保护膜具有至少两层不同的介电常数，并且将反应性气体顺序地供应到处理室。 由此形成的氮化物层具有低氢含量，良好的密度和抗氧化性。

    Semiconductor device having triple-well
    6.
    发明授权
    Semiconductor device having triple-well 有权
    具有三重阱的半导体器件

    公开(公告)号：US06225199B1

    公开(公告)日：2001-05-01

    申请号：US09348381

    申请日：1999-07-07

    申请人： Jae-Jong Han ,  Doo-Hyun Hwang ,  Byung-Kee Kim ,  Beung-Keun Lee

    发明人： Jae-Jong Han ,  Doo-Hyun Hwang ,  Byung-Kee Kim ,  Beung-Keun Lee

    IPC分类号： H01L21265

    CPC分类号： H01L21/761 ,  H01L27/10894

    摘要： The triple-well according to the present invention reduces a photo process forming a well isolation region which is used in a method for forming a prior well. That is, two times of photo processes are reduced to be one time, thereby simplifying a method for forming a triple-well of the DRAM device and reducing time and expenditure.

    摘要翻译： 根据本发明的三重阱减少了形成井分离区域的光刻工艺，其用于形成先前井的方法。 也就是说，将两次照相处理减少为一次，从而简化了用于形成DRAM器件的三阱的方法并减少了时间和费用。

    Methods and apparatus for forming thin films for semiconductor devices
    8.
    发明授权
    Methods and apparatus for forming thin films for semiconductor devices 有权
    用于形成半导体器件薄膜的方法和装置

    公开(公告)号：US07273822B2

    公开(公告)日：2007-09-25

    申请号：US11038324

    申请日：2005-01-19

    申请人： Jae-Hyun Yeo ,  Young-Wook Park ,  Ki-Chul Kim ,  Jae-Jong Han

    发明人： Jae-Hyun Yeo ,  Young-Wook Park ,  Ki-Chul Kim ,  Jae-Jong Han

    IPC分类号： H01L21/31

    CPC分类号： C23C16/44 ,  H01L21/28562 ,  H01L21/3141 ,  H01L21/31604 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/31691

    摘要： Methods and apparatus are provided for forming thin films for semiconductor devices, which enable supplying and removing reactants containing constituent elements of a thin film to be formed, by preheating and supplying a process gas and a purging gas at a predetermined temperature in forming the thin film on a substrate. For example, a method for forming a thin film includes supplying a first reactant to a chamber to chemically adsorb the first reactant onto a substrate, the first reactant being bubbled by a first gas that is preheated, purging the chamber to remove residues on the substrate having the first reactant chemically adsorbed, and forming the thin film by a means of chemical displacement by supplying a second reactant to the chamber to chemically adsorb the second reactant onto the substrate.

    摘要翻译： 提供了用于形成用于半导体器件的薄膜的方法和装置，其能够通过在预定温度下预热和提供处理气体和净化气体来形成薄膜来提供和除去含有待形成的薄膜的构成元素的反应物 在基板上。 例如，用于形成薄膜的方法包括将第一反应物供应到室以化学吸附第一反应物到基底上，第一反应物被预热的第一气体鼓泡，清洗室以除去基底上的残留物 使所述第一反应物被化学吸附，并且通过向所述室供应第二反应物以化学吸附所述第二反应物到所述基底上，通过化学位移形成所述薄膜。

    Method of manufacturing a semiconductor device including alignment mark
    10.
    发明授权
    Method of manufacturing a semiconductor device including alignment mark 有权
    制造包括对准标记的半导体器件的方法

    公开(公告)号：US06794263B1

    公开(公告)日：2004-09-21

    申请号：US10367931

    申请日：2003-02-19

    申请人： Kong-Soo Lee ,  Young-Wook Park ,  Jae-Jong Han ,  Gi-Hyun Hwang ,  Kyoung-Seok Kim ,  Sung-Eui Kim ,  Seung-Mok Shin

    发明人： Kong-Soo Lee ,  Young-Wook Park ,  Jae-Jong Han ,  Gi-Hyun Hwang ,  Kyoung-Seok Kim ,  Sung-Eui Kim ,  Seung-Mok Shin

    IPC分类号： H01L2176

    CPC分类号： H01L23/544 ,  G03F9/7076 ,  G03F9/708 ,  G03F9/7084 ,  H01L21/76229 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/959 ,  Y10S438/975 ,  H01L2924/00

    摘要： A method of inhibiting pit occurrence on a semiconductor substrate during manufacture of a semiconductor device includes forming an isolation using a shallow trench isolation (STI) method in a semiconductor substrate, forming an insulation layer on an entire surface of the semiconductor substrate having the isolation, implanting ions into the semiconductor substrate using the insulation layer as a buffer layer, annealing the semiconductor substrate using a rapid thermal annealing (RTA) process, forming a photoresist layer on the insulation layer and then forming an opening in the photoresist layer to expose an underlayer thereof, forming an align key by etching the underlayer at the opening, and removing the photoresist layer and the insulation layer. Alternatively, the thickness of the insulation layer may be reduced to prevent the occurrence of pits on active areas of the semiconductor substrate.

    摘要翻译： 在半导体器件的制造期间抑制半导体衬底上的凹坑产生的方法包括在半导体衬底中形成使用浅沟槽隔离（STI）方法的隔离，在具有隔离的半导体衬底的整个表面上形成绝缘层， 使用绝缘层作为缓冲层将离子注入到半导体衬底中，使用快速热退火（RTA）工艺对半导体衬底进行退火，在绝缘层上形成光致抗蚀剂层，然后在光刻胶层中形成开口以暴露底层 通过在开口处蚀刻底层形成对准键，以及去除光致抗蚀剂层和绝缘层。 或者，可以减小绝缘层的厚度，以防止在半导体衬底的有源区域上出现凹坑。