公开(公告)号：US20100221867A1

公开(公告)日：2010-09-02

申请号：US12436249

申请日：2009-05-06

申请人： Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Harold J. Hovel ,  Daniel A. Inns ,  Jeehwan Kim ,  Devendra K. Sadana ,  Katherine L. Saenger ,  Ghavam G. Shahidi

发明人： Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Harold J. Hovel ,  Daniel A. Inns ,  Jeehwan Kim ,  Devendra K. Sadana ,  Katherine L. Saenger ,  Ghavam G. Shahidi

IPC分类号： H01L31/0376 ,  H01L21/762

CPC分类号： H01L31/03921 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/02667 ,  H01L21/7624 ,  H01L21/76245 ,  H01L21/76262 ,  H01L31/046 ,  H01L31/0463 ,  H01L31/0465 ,  H01L31/1872 ,  Y02E10/50 ,  Y02P70/521

摘要： A lost cost method for fabricating SOI substrates is provided. The method includes forming a stack of p-type doped amorphous Si-containing layers on a semiconductor region of a substrate by utilizing an evaporation deposition process. A solid phase recrystallization step is then performed to convert the amorphous Si-containing layers within the stack into a stack of p-type doped single crystalline Si-containing layers. After recrystallization, the single crystalline Si-containing layers are subjected to anodization and at least an oxidation step to form an SOI substrate. Solar cells and/or other semiconductor devices can be formed on the upper surface of the inventive SOI substrate.

摘要翻译： 提供了一种用于制造SOI衬底的损耗成本方法。 该方法包括通过利用蒸发沉积工艺在衬底的半导体区域上形成一层p型掺杂的非晶态含Si层。 然后进行固相重结晶步骤，以将叠层内的非晶态含硅层转化为p型掺杂单晶含Si层的堆叠。 重结晶后，对单晶含Si层进行阳极氧化和至少氧化步骤以形成SOI衬底。 太阳能电池和/或其他半导体器件可以形成在本发明的SOI衬底的上表面上。

公开(公告)号：US20090217967A1

公开(公告)日：2009-09-03

申请号：US12039826

申请日：2008-02-29

申请人： Harold J. Hovel ,  Joel P. de Souza ,  Devendra K. Sadana

发明人： Harold J. Hovel ,  Joel P. de Souza ,  Devendra K. Sadana

IPC分类号： H01L31/042 ,  H01L31/00 ,  H01L21/02

CPC分类号： H01L31/035281 ,  B82Y20/00 ,  H01L31/022425 ,  H01L31/0296 ,  H01L31/0304 ,  H01L31/18 ,  Y02E10/544 ,  Y02P70/521

摘要： Embodiments of the present invention provide a solar energy converter, which includes a silicon layer having at least two regions of a first and a second conductivity type that form a P-N junction, at least a portion of the silicon layer being porous, and pores in the portion of porous silicon containing a semiconductor material, the semiconductor material being different from silicon; and a first and a second electrode being placed at a bottom and a top surface of the silicon layer respectively. Methods of manufacturing the same are also provided.

摘要翻译： 本发明的实施例提供了一种太阳能转换器，其包括具有形成PN结的至少两个第一和第二导电类型的区域的硅层，至少一部分硅层是多孔的，并且孔中的孔 含有半导体材料的多孔硅的部分，所述半导体材料与硅不同; 以及分别设置在硅层的底部和顶面的第一和第二电极。 还提供了制造方法。

公开(公告)号：US09059245B2

公开(公告)日：2015-06-16

申请号：US13483781

申请日：2012-05-30

申请人： Tze-Chiang Chen ,  Joel P. de Souza ,  Devendra K. Sadana ,  Ghavam G. Shahidi

发明人： Tze-Chiang Chen ,  Joel P. de Souza ,  Devendra K. Sadana ,  Ghavam G. Shahidi

IPC分类号： H01L21/76 ,  H01L21/762

CPC分类号： H01L21/76243

摘要： Semiconductor-on-insulator (SOI) substrates including a buried oxide (BOX) layer having a thickness of less than 300 Å are provided. The (SOI) substrates having the thin BOX layer are provided using a method including a step in which oxygen ions are implanted at high substrate temperatures (greater than 600° C.), and at a low implant energy (less than 40 keV). An anneal step in an oxidizing atmosphere follows the implant step and is performed at a temperature less than 1250° C. The anneal step in oxygen containing atmosphere converts the region containing implanted oxygen atoms formed by the implant step into a BOX having a thickness of less than 300 Å. In some instances, the top semiconductor layer of the SOI substrate has a thickness of less than 300 Å.

摘要翻译： 提供了包括厚度小于300埃的掩埋氧化物（BOX）层的绝缘体上半导体（SOI）衬底。 使用包括以高衬底温度（大于600℃）和低注入能量（小于40keV）注入氧离子的步骤的方法提供具有薄BOX层的（SOI）衬底。 氧化气氛中的退火步骤遵循注入步骤，并且在低于1250℃的温度下进行。含氧气氛中的退火步骤将包含由注入步骤形成的注入的氧原子的区域转换成厚度较小的BOX 比300Å。 在一些情况下，SOI衬底的顶部半导体层具有小于300埃的厚度。

公开(公告)号：US20130320483A1

公开(公告)日：2013-12-05

申请号：US13483781

申请日：2012-05-30

申请人： Tze-Chiang Chen ,  Joel P. de Souza ,  Devendra K. Sadana ,  Ghavam G. Shahidi

发明人： Tze-Chiang Chen ,  Joel P. de Souza ,  Devendra K. Sadana ,  Ghavam G. Shahidi

IPC分类号： H01L21/762 ,  H01L29/02

CPC分类号： H01L21/76243

摘要： Semiconductor-on-insulator (SOI) substrates including a buried oxide (BOX) layer having a thickness of less than 300 Å are provided. The (SOI) substrates having the thin BOX layer are provided using a method including a step in which oxygen ions are implanted at high substrate temperatures (greater than 600° C.), and at a low implant energy (less than 40 keV). An anneal step in an oxidizing atmosphere follows the implant step and is performed at a temperature less than 1250° C. The anneal step in oxygen containing atmosphere converts the region containing implanted oxygen atoms formed by the implant step into a BOX having a thickness of less than 300 Å. In some instances, the top semiconductor layer of the SOI substrate has a thickness of less than 300 Å.

摘要翻译： 提供了包括厚度小于300埃的掩埋氧化物（BOX）层的绝缘体上半导体（SOI）衬底。 使用包括以高衬底温度（大于600℃）和低注入能量（小于40keV）注入氧离子的步骤的方法提供具有薄BOX层的（SOI）衬底。 氧化气氛中的退火步骤遵循注入步骤，并且在低于1250℃的温度下进行。含氧气氛中的退火步骤将包含由注入步骤形成的注入的氧原子的区域转换成厚度较小的BOX 比300Å。 在一些情况下，SOI衬底的顶部半导体层具有小于300埃的厚度。

公开(公告)号：US07365399B2

公开(公告)日：2008-04-29

申请号：US11333074

申请日：2006-01-17

申请人： Joel P. de Souza ,  Keith E. Fogel ,  Brian J. Greene ,  Devendra K. Sadana ,  Haining S. Yang

发明人： Joel P. de Souza ,  Keith E. Fogel ,  Brian J. Greene ,  Devendra K. Sadana ,  Haining S. Yang

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC分类号： H01L29/32 ,  H01L21/0203 ,  H01L21/76259 ,  H01L29/1033 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/78

摘要： A semiconducting material that has all the advantages of prior art SOI substrates including, for example, low parasitic capacitance and leakage, without having floating body effects is provided. More specifically, the present invention provides a Semiconductor-on-Pores (SOP) material that includes a top semiconductor layer and a bottom semiconductor layer, wherein the semiconductor layers are separated in at least one region by a porous semiconductor material. Semiconductor structures including the SOP material as a substrate as well as a method of fabricating the SOP material are also provided. The method includes forming a p-type region with a first semiconductor layer, converting the p-type region to a porous semiconductor material, sealing the upper surface of the porous semiconductor material by annealing, and forming a second semiconductor layer atop the porous semiconductor material.

摘要翻译： 提供了具有现有技术的SOI衬底的所有优点的半导体材料，包括例如低寄生电容和泄漏，而不具有浮体效应。 更具体地说，本发明提供一种包括顶部半导体层和底部半导体层的半导体激光器（SOP）材料，其中半导体层通过多孔半导体材料在至少一个区域中分离。 还提供了包括作为基板的SOP材料的半导体结构以及制造SOP材料的方法。 该方法包括：形成具有第一半导体层的p型区域，将p型区域转换为多孔半导体材料，通过退火密封多孔半导体材料的上表面，以及在多孔半导体材料的顶部形成第二半导体层 。

公开(公告)号：US20120305989A1

公开(公告)日：2012-12-06

申请号：US13570989

申请日：2012-08-09

申请人： Joel P. de Souza ,  Keith E. Fogel ,  Edward W. Kiewra ,  Steven J. Koester ,  Christopher C. Parks ,  Devendra K. Sadana ,  Shahab Siddiqui

发明人： Joel P. de Souza ,  Keith E. Fogel ,  Edward W. Kiewra ,  Steven J. Koester ,  Christopher C. Parks ,  Devendra K. Sadana ,  Shahab Siddiqui

IPC分类号： H01L29/78

CPC分类号： H01L21/28264 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of preventing surface decomposition of a III-V compound semiconductor is provided. The method includes forming a silicon film having a thickness from 10 Å to 400 Å on a surface of an III-V compound semiconductor. After forming the silicon film onto the surface of the III-V compound semiconductor, a high performance semiconductor device including, for example, a MOSFET, can be formed on the capped/passivated III-V compound semiconductor. During the MOSFET fabrication, a high k dielectric can be formed on the capped/passivated III-V compound semiconductor and thereafter, activated source and drain regions can be formed into the III-V compound semiconductor.

摘要翻译： 提供了防止III-V族化合物半导体的表面分解的方法。 该方法包括在III-V族化合物半导体的表面上形成厚度为从至400的硅膜。 在III-V族化合物半导体的表面上形成硅膜之后，可以在封盖/钝化的III-V化合物半导体上形成包括例如MOSFET的高性能半导体器件。 在MOSFET制造期间，可以在封盖/钝化的III-V化合物半导体上形成高k电介质，此后可以将激活的源极和漏极区域形成为III-V族化合物半导体。

公开(公告)号：US20120295417A1

公开(公告)日：2012-11-22

申请号：US13109567

申请日：2011-05-17

申请人： Thomas N. Adam ,  Katherina E. Babich ,  Stephen W. Bedell ,  Joel P. de Souza ,  Gerald W. Gibson ,  Alexander Reznicek ,  Devendra K. Sadana ,  Seshadri Subbanna

发明人： Thomas N. Adam ,  Katherina E. Babich ,  Stephen W. Bedell ,  Joel P. de Souza ,  Gerald W. Gibson ,  Alexander Reznicek ,  Devendra K. Sadana ,  Seshadri Subbanna

IPC分类号： H01L21/20

CPC分类号： H01L29/66628 ,  H01L21/0237 ,  H01L21/02524 ,  H01L21/02639 ,  H01L29/165 ,  H01L29/78

摘要： A method of controlling the nucleation rate (i.e., incubation time) of dissimilar materials in an epitaxial growth chamber that can favor high growth rates and can be compatible with low temperature growth is provided. The nucleation rate of dissimilar materials is controlled in an epitaxial growth chamber by altering the nucleation rate for the growth of a given material film, relative to single crystal growth of the same material film, by choosing an appropriate masking material with a given native nucleation characteristic, or by modifying the surface of the masking layer to achieve the appropriate nucleation characteristic. Alternatively, nucleation rate control can be achieved by modifying the surface of selected areas of a semiconductor substrate relative to other areas in which an epitaxial semiconductor material will be subsequently formed.

摘要翻译： 提供了一种控制外延生长室中不同材料的成核速率（即孵育时间）的方法，其可以有利于高生长速率并且可以与低温生长相容。 通过选择具有给定的天然成核特性的合适的掩蔽材料，通过相对于相同材料膜的单晶生长改变给定材料膜的生长的成核速率，在外延生长室中控制不同材料的成核速率 ，或通过改变掩模层的表面以获得适当的成核特性。 或者，可以通过相对于其后将形成外延半导体材料的其它区域修改半导体衬底的选定区域的表面来实现成核速率控制。

公开(公告)号：US08273649B2

公开(公告)日：2012-09-25

申请号：US12272129

申请日：2008-11-17

申请人： Joel P. de Souza ,  Keith E. Fogel ,  Edward W. Kiewra ,  Steven J. Koester ,  Christopher C. Parks ,  Devendra K. Sadana ,  Shahab Siddiqui

发明人： Joel P. de Souza ,  Keith E. Fogel ,  Edward W. Kiewra ,  Steven J. Koester ,  Christopher C. Parks ,  Devendra K. Sadana ,  Shahab Siddiqui

IPC分类号： H01L21/28 ,  H01L21/3205

CPC分类号： H01L21/28264 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of preventing surface decomposition of a III-V compound semiconductor is provided. The method includes forming a silicon film having a thickness from 10 Å to 400 Å on a surface of an III-V compound semiconductor. After forming the silicon film onto the surface of the III-V compound semiconductor, a high performance semiconductor device including, for example, a MOSFET, can be formed on the capped/passivated III-V compound semiconductor. During the MOSFET fabrication, a high k dielectric can be formed on the capped/passivated III-V compound semiconductor and thereafter, activated source and drain regions can be formed into the III-V compound semiconductor.

摘要翻译： 提供了防止III-V族化合物半导体的表面分解的方法。 该方法包括在III-V族化合物半导体的表面上形成厚度为从至400的硅膜。 在III-V族化合物半导体的表面上形成硅膜之后，可以在封盖/钝化的III-V化合物半导体上形成包括例如MOSFET的高性能半导体器件。 在MOSFET制造期间，可以在封盖/钝化的III-V化合物半导体上形成高k电介质，此后可以将激活的源极和漏极区域形成为III-V族化合物半导体。

公开(公告)号：US20120156861A1

公开(公告)日：2012-06-21

申请号：US13405760

申请日：2012-02-27

申请人： Joel P. de Souza ,  John A. Ott ,  Alexander Reznicek ,  Devendra K. Sadana ,  Katherine L. Saenger

发明人： Joel P. de Souza ,  John A. Ott ,  Alexander Reznicek ,  Devendra K. Sadana ,  Katherine L. Saenger

IPC分类号： H01L21/302

CPC分类号： H01L21/187 ,  H01L21/76251

摘要： Methods for removing or reducing the thickness of a material layer remaining at Si-Si interfaces after silicon wafer bonding. The methods include an anneal which is performed at a temperature sufficient to dissolve oxide, yet not melt silicon.

摘要翻译： 在硅晶片接合之后去除或减少残留在Si-Si界面处的材料层的厚度的方法。 所述方法包括在足以溶解氧化物但不熔融硅的温度下进行的退火。

公开(公告)号：US07842940B2

公开(公告)日：2010-11-30

申请号：US12062164

申请日：2008-04-03

申请人： Joel P. de Souza ,  Keith E. Fogel ,  Brian J. Greene ,  Devendra K. Sadana ,  Haining S. Yang

发明人： Joel P. de Souza ,  Keith E. Fogel ,  Brian J. Greene ,  Devendra K. Sadana ,  Haining S. Yang

IPC分类号： H01L31/00

CPC分类号： H01L29/32 ,  H01L21/0203 ,  H01L21/76259 ,  H01L29/1033 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/78

摘要： A semiconducting material that has all the advantages of prior art SOI substrates including, for example, low parasitic capacitance and leakage, without having floating body effects is provided. More specifically, the present invention provides a Semiconductor-on-Pores (SOP) material that includes a top semiconductor layer and a bottom semiconductor layer, wherein the semiconductor layers are separated in at least one region by a porous semiconductor material. Semiconductor structures including the SOP material as a substrate as well as a method of fabricating the SOP material are also provided. The method includes forming a p-type region with a first semiconductor layer, converting the p-type region to a porous semiconductor material, sealing the upper surface of the porous semiconductor material by annealing, and forming a second semiconductor layer atop the porous semiconductor material.

摘要翻译： 提供了具有现有技术的SOI衬底的所有优点的半导体材料，包括例如低寄生电容和泄漏，而不具有浮体效应。 更具体地说，本发明提供一种包括顶部半导体层和底部半导体层的半导体激光器（SOP）材料，其中半导体层通过多孔半导体材料在至少一个区域中分离。 还提供了包括作为基板的SOP材料的半导体结构以及制造SOP材料的方法。 该方法包括：形成具有第一半导体层的p型区域，将p型区域转换为多孔半导体材料，通过退火密封多孔半导体材料的上表面，以及在多孔半导体材料的顶部形成第二半导体层 。